[PATCH] RISC-V: Fix disassemble for c.li, c.andi and c.addiw
Palmer Dabbelt
palmer@dabbelt.com
Wed May 3 16:54:00 GMT 2017
From: Kito Cheng <kito.cheng@gmail.com>
ChangeLog
2017-05-03 Kito Cheng <kito.cheng@gmail.com>
* riscv-dis.c (print_insn_args): Handle 'Co' operands.
---
opcodes/ChangeLog | 4 ++++
opcodes/riscv-dis.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 355a162..ea0902f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-03 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-dis.c (print_insn_args): Handle 'Co' operands.
+
2017-05-01 Michael Clark <michaeljclark@mac.com>
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d70..bb53463 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'i':
print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
break;
+ case 'o':
case 'j':
print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
break;
--
2.10.2
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