FW: [PATCHv2] Implementing ARC NPS-400 Ultra Ip and Miscellaneous instructions
Rinat Zelig
rinat@mellanox.com
Wed Mar 22 11:20:00 GMT 2017
Hi
Add Ultra Ip and Miscellaneous instructions format. Following changes from last patch:
1. replace spaces with tabs.
2. fix insert extract functions prototype.
Regards
Rinat
opcodes/Changelog
* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include/Changelog
* opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas/Changelog
* testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
---
gas/ChangeLog | 5 ++
gas/testsuite/gas/arc/nps400-12.d | 59 +++++++++++++++++++
gas/testsuite/gas/arc/nps400-12.s | 71 ++++++++++++++++++++++
include/ChangeLog | 4 +
include/opcode/arc.h | 2 +
opcodes/ChangeLog | 10 +++
opcodes/arc-nps400-tbl.h | 70 ++++++++++++++++++++++
opcodes/arc-opc.c | 116 ++++++++++++++++++++++++++++++++++--
8 files changed, 330 insertions(+), 7 deletions(-) create mode 100644 gas/testsuite/gas/arc/nps400-12.d create mode 100644 gas/testsuite/gas/arc/nps400-12.s
diff --git a/gas/testsuite/gas/arc/nps400-12.d b/gas/testsuite/gas/arc/nps400-12.d
new file mode 100644
index 0000000..47e954f
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-12.d
@@ -0,0 +1,59 @@
+#as: -mcpu=nps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 3815 0042 whash r2,\[cm:r0\],r1
+ 4: 3b15 0385 whash r5,\[cm:r3\],r14
+ 8: 3815 007e whash 0,\[cm:r0\],r1
+ c: 3b15 03be whash 0,\[cm:r3\],r14
+ 10: 3855 01c2 whash r2,\[cm:r0\],0x7
+ 14: 3855 01fe whash 0,\[cm:r0\],0x7
+ 18: 3855 0002 whash r2,\[cm:r0\],0x40
+ 1c: 3855 003e whash 0,\[cm:r0\],0x40
+ 20: 4822 4000 mcmp r0,\[cm:r0\],\[cm:r1\],r1
+ 24: 4822 6000 mcmp\.s r0,\[cm:r0\],\[cm:r1\],r1
+ 28: 4822 4080 mcmp\.m r0,\[cm:r0\],\[cm:r1\],r1
+ 2c: 4822 6080 mcmp\.s\.m r0,\[cm:r0\],\[cm:r1\],r1
+ 30: 4822 0000 mcmp r0,\[cm:r0,r0\],\[cm:r1\],r1
+ 34: 4822 2000 mcmp\.s r0,\[cm:r0,r0\],\[cm:r1\],r1
+ 38: 4822 0080 mcmp\.m r0,\[cm:r0,r0\],\[cm:r1\],r1
+ 3c: 4822 2080 mcmp\.s\.m r0,\[cm:r0,r0\],\[cm:r1\],r1
+ 40: 4822 4100 mcmp r0,\[cm:r0,0x4\],\[cm:r1\],r1
+ 44: 4822 6100 mcmp\.s r0,\[cm:r0,0x4\],\[cm:r1\],r1
+ 48: 4822 4180 mcmp\.m r0,\[cm:r0,0x4\],\[cm:r1\],r1
+ 4c: 4822 6180 mcmp\.s\.m r0,\[cm:r0,0x4\],\[cm:r1\],r1
+ 50: 4822 4200 mcmp r0,\[cm:r0,0x8\],\[cm:r1\],r1
+ 54: 4822 4300 mcmp r0,\[cm:r0,0xc\],\[cm:r1\],r1
+ 58: 4822 c004 mcmp r0,\[cm:r0\],\[cm:r1\],0x4
+ 5c: 4822 e004 mcmp\.s r0,\[cm:r0\],\[cm:r1\],0x4
+ 60: 4822 c084 mcmp\.m r0,\[cm:r0\],\[cm:r1\],0x4
+ 64: 4822 e088 mcmp\.s\.m r0,\[cm:r0\],\[cm:r1\],0x8
+ 68: 4822 c07f mcmp r0,\[cm:r0\],\[cm:r1\],0x7f
+ 6c: 4822 c204 mcmp r0,\[cm:r0,0x8\],\[cm:r1\],0x4
+ 70: 4822 e204 mcmp\.s r0,\[cm:r0,0x8\],\[cm:r1\],0x4
+ 74: 4822 c284 mcmp\.m r0,\[cm:r0,0x8\],\[cm:r1\],0x4
+ 78: 4822 e284 mcmp\.s\.m r0,\[cm:r0,0x8\],\[cm:r1\],0x4
+ 7c: 4822 802e mcmp r0,\[cm:r0,r0\],\[cm:r1\],0x2e
+ 80: 4822 a046 mcmp\.s r0,\[cm:r0,r0\],\[cm:r1\],0x46
+ 84: 4822 80c8 mcmp\.m r0,\[cm:r0,r0\],\[cm:r1\],0x48
+ 88: 4822 a0fd mcmp\.s\.m r0,\[cm:r0,r0\],\[cm:r1\],0x7d
+ 8c: 3856 003e asri 0,r0
+ 90: 3856 007e asri\.core 0,r0
+ 94: 3856 00be asri\.clsr 0,r0
+ 98: 3856 00fe asri\.all 0,r0
+ 9c: 3856 013e asri\.gic 0,r0
+ a0: 3856 017e rspi\.gic 0,r0
+ a4: 385b 003e wkup 0,r0
+ a8: 385b 013e wkup\.cl
+ ac: 3a2f 0024 getsti r2,\[cm:r0\]
+ b0: 3e2f 7024 getsti 0,\[cm:r0\]
+000000b4 <label>:
+ b4: 3a2f 0025 getrtc r2,\[cm:r0\]
+ b8: 3e2f 7025 getrtc 0,\[cm:r0\]
+ bc: 07f8 ffd5 bnj -8
+ c0: 07f4 ffd7 bnm -12
+ c4: 07f0 ffd8 bnt -16
diff --git a/gas/testsuite/gas/arc/nps400-12.s b/gas/testsuite/gas/arc/nps400-12.s
new file mode 100644
index 0000000..aa19b30
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-12.s
@@ -0,0 +1,71 @@
+ .text
+
+ ; Miscellaneous
+ ; whash
+ whash r2,[cm:r0],r1
+ whash r5,[cm:r3],r14
+ whash 0,[cm:r0],r1
+ whash 0,[cm:r3],r14
+ whash r2,[cm:r0],7
+ whash 0,[cm:r0],7
+ whash r2,[cm:r0],64
+ whash 0,[cm:r0],64
+
+ ; mcmp
+ mcmp r0,[cm:r0],[cm:r1],r1
+ mcmp.s r0,[cm:r0],[cm:r1],r1
+ mcmp.m r0,[cm:r0],[cm:r1],r1
+ mcmp.s.m r0,[cm:r0],[cm:r1],r1
+
+ mcmp r0,[cm:r0,r0],[cm:r1],r1
+ mcmp.s r0,[cm:r0,r0],[cm:r1],r1
+ mcmp.m r0,[cm:r0,r0],[cm:r1],r1
+ mcmp.s.m r0,[cm:r0,r0],[cm:r1],r1
+
+ mcmp r0,[cm:r0,4],[cm:r1],r1
+ mcmp.s r0,[cm:r0,4],[cm:r1],r1
+ mcmp.m r0,[cm:r0,4],[cm:r1],r1
+ mcmp.s.m r0,[cm:r0,4],[cm:r1],r1
+ mcmp r0,[cm:r0,8],[cm:r1],r1
+ mcmp r0,[cm:r0,12],[cm:r1],r1
+
+ mcmp r0,[cm:r0],[cm:r1],4
+ mcmp.s r0,[cm:r0],[cm:r1],4
+ mcmp.m r0,[cm:r0],[cm:r1],4
+ mcmp.s.m r0,[cm:r0],[cm:r1],8
+ mcmp r0,[cm:r0],[cm:r1],127
+
+ mcmp r0,[cm:r0,8],[cm:r1],4
+ mcmp.s r0,[cm:r0,8],[cm:r1],4
+ mcmp.m r0,[cm:r0,8],[cm:r1],4
+ mcmp.s.m r0,[cm:r0,8],[cm:r1],4
+
+ mcmp r0,[cm:r0,r0],[cm:r1],46
+ mcmp.s r0,[cm:r0,r0],[cm:r1],70
+ mcmp.m r0,[cm:r0,r0],[cm:r1],72
+ mcmp.s.m r0,[cm:r0,r0],[cm:r1],125
+
+ ;asri
+ asri 0, r0
+ asri.core 0, r0
+ asri.clsr 0,r0
+ asri.all 0,r0
+ asri.gic 0,r0
+ rspi.gic 0,r0
+
+ ;wkup
+ wkup 0,r0
+ wkup.cl
+
+ ;getsti
+ getsti r2,[cm:r0]
+ getsti 0,[cm:r0]
+label:
+ ;getrtc
+ getrtc r2,[cm:r0]
+ getrtc 0,[cm:r0]
+
+ ;b<cc>
+ bnj label
+ bnm label
+ bnt label
diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 3914dc0..d0ea27e 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -68,6 +68,7 @@ typedef enum
LOGICAL,
LOOP,
MEMORY,
+ MISC,
MOVE,
MPY,
NET,
@@ -77,6 +78,7 @@ typedef enum
PUSH,
STORE,
SUB,
+ ULTRAIP,
XY
} insn_class_t;
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 9952fb2..4bd95c1 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -905,6 +905,76 @@ XLDST_LIKE("xst", 0xe)
/* cp32<.na> [xd:src1,src2,src2,src2], [cm:src2] */ { "cp32", 0x48078181, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
+/* Ultra IP Instructions. */
+
+/* uip<.na> dst, [cm:src2], [cm:src1] */ { "uip", 0x480740a2,
+0xf81fc1e3, ARC_OPCODE_ARC700, ULTRAIP, NPS400, { NPS_R_DST_3B, BRAKET,
+NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON,
+NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
+
+/* uip<.na> dst, [cm:src2], [cm:src1], src2 */ { "uip", 0x480700a2,
+0xf81fc1e3, ARC_OPCODE_ARC700, ULTRAIP, NPS400, { NPS_R_DST_3B, BRAKET,
+NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON,
+NPS_DPI_SRC1_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_NA }},
+
+/* Miscellaneous Instructions. */
+
+/* whash dst,[cm:src1],src2*/
+{ "whash", 0x38150000, 0xf8ff0000, ARC_OPCODE_ARC700, MISC, NPS400, {
+RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RC }, { 0 }},
+
+/* whash 0,[cm:src1],src2 */
+{ "whash", 0x3815003e, 0xf8ff003f, ARC_OPCODE_ARC700, MISC, NPS400, {
+ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RC }, { 0 }},
+
+/* whash dst,[cm:src1],size */
+{ "whash", 0x38550000, 0xf8ff0000, ARC_OPCODE_ARC700, MISC, NPS400, {
+RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, NPS_WHASH_SIZE }, { 0 }},
+
+/* whash 0,[cm:src1],size */
+{ "whash", 0x3855003e, 0xf8ff003f, ARC_OPCODE_ARC700, MISC, NPS400, {
+ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, NPS_WHASH_SIZE }, { 0 }},
+
+/* mcmp<.s><.m> dst,[cm:src1],[cm:src2],src2 */ { "mcmp", 0x48024000,
+0xf81fdf7f, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET,
+NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON,
+NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
+
+/* mcmp<.s><.m> dst,[cm:src1,src1],[cm:src2],src2 */ { "mcmp",
+0x48020000, 0xf81fdf7f, ARC_OPCODE_ARC700, MISC, NPS400, {
+NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, NPS_DPI_SRC1_3B,
+BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup,
+NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
+
+/* mcmp.<s><.m> dst,[cm:src1,offset],[cm:src2],src2 */ { "mcmp",
+0x48024000, 0xf81fc000, ARC_OPCODE_ARC700, MISC, NPS400, {
+NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B,
+NPS_MISC_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B,
+BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
+
+/* mcmp<.s><.m> dst,[cm:src1],[cm: src2],size */ { "mcmp", 0x4802c000,
+0xf81fcf00, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET,
+NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON,
+NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
+
+/* mcmp<.s><.m> dst,[cm:src1,offset],[cm:src2],size */ { "mcmp",
+0x4802c000, 0xf81fc000, ARC_OPCODE_ARC700, MISC, NPS400, {
+NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B,
+NPS_MISC_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B,
+BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
+
+/* mcmp<.s><.m> dst,[cm:src1,src1],[cm:src2],size */ { "mcmp",
+0x48028000, 0xf81fdf00, ARC_OPCODE_ARC700, MISC, NPS400, {
+NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, NPS_DPI_SRC1_3B,
+BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup,
+NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
+
+#define ASRI_LIKE(SUBOP2, FLAG) \
+{ "asri", (0x3856003e | (SUBOP2 << 6)), 0xf8ff8fff, ARC_OPCODE_ARC700,
+MISC, NPS400, { ZA, RB }, { FLAG }},
+
+ASRI_LIKE (0x0, 0)
+ASRI_LIKE (0x1, C_NPS_CORE)
+ASRI_LIKE (0x2, C_NPS_CLSR)
+ASRI_LIKE (0x3, C_NPS_ALL)
+ASRI_LIKE (0x4, C_NPS_GIC)
+
+/* rspi.gic 0,src1 */
+{ "rspi", 0x3856017e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, {
+ZA, RB }, { C_NPS_RSPI_GIC }},
+
+/* wkup.cl */
+{ "wkup", 0x385b013e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { 0
+}, { C_NPS_CL }},
+
+/* wkup 0, src2 */
+{ "wkup", 0x385b003e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, {
+ZA, RC }, { 0 }},
+
+/* getsti dst,[cm:src2] */
+{ "getsti", 0x382f0024, 0xf8ff803f, ARC_OPCODE_ARC700, MISC, NPS400, {
+RB, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
+
+/* getsti 0, [cm:src2] */
+{ "getsti", 0x3e2f7024, 0xfffff03f, ARC_OPCODE_ARC700, MISC, NPS400, {
+ZA, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
+
+/* getrtc dst,[cm:src2] */
+{ "getrtc", 0x382f0025, 0xf8ff803f, ARC_OPCODE_ARC700, MISC, NPS400, {
+RB, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
+
+/* getrtc 0, [cm:src2] */
+{ "getrtc", 0x3e2f7025, 0xfffff03f, ARC_OPCODE_ARC700, MISC, NPS400, {
+ZA, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
+
/* Atomic Operations. */
/* exc<.di><.f> a,a,[xa:b] */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index f4a03f8..ec411d4 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -896,6 +896,29 @@ extract_nps_imm_entry (unsigned long long insn ATTRIBUTE_UNUSED,
return (1 << (imm_entry + 4));
}
+
+static unsigned long long
+insert_nps_size_16bit (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED) {
+ if ((value < 1) || (value > 64))
+ {
+ *errmsg = _("Invalid size value must be on range 1-64.");
+ value = 0;
+ }
+ value = value & 0x3f;
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long int
+extract_nps_size_16bit (unsigned long long insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) {
+ return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64; }
+
#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
static unsigned long long \
insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
@@ -1197,6 +1220,27 @@ extract_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
return value1;
}
+static unsigned long long
+insert_nps_misc_imm_offset (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED) {
+ if (value & 0x3)
+ {
+ *errmsg = _("Invalid position, should be 0,4, 8,...124.");
+ value = 0;
+ }
+ insn |= (value << 6);
+ return insn;
+}
+
+static long long int
+extract_nps_misc_imm_offset (unsigned long long insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) {
+ return ((insn >> 8) & 0x1f) * 4;
+}
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -1264,9 +1308,15 @@ const struct arc_flag_operand arc_flag_operands[] =
{ "ls", 14, 5, 0, 1 },
#define F_PNZ (F_LS + 1)
{ "pnz", 15, 5, 0, 1 },
+#define F_NJ (F_PNZ + 1)
+ { "nj", 21, 5, 0, 1 },
+#define F_NM (F_NJ + 1)
+ { "nm", 23, 5, 0, 1 },
+#define F_NO_T (F_NM + 1)
+ { "nt", 24, 5, 0, 1 },
/* FLAG. */
-#define F_FLAG (F_PNZ + 1)
+#define F_FLAG (F_NO_T + 1)
{ "f", 1, 1, 15, 1 },
#define F_FFAKE (F_FLAG + 1)
{ "f", 0, 0, 0, 1 },
@@ -1368,7 +1418,13 @@ const struct arc_flag_operand arc_flag_operands[] = #define F_NPS_NA (F_NPS_CL + 1)
{ "na", 1, 1, 9, 1 },
-#define F_NPS_FLAG (F_NPS_NA + 1)
+#define F_NPS_SR (F_NPS_NA + 1)
+ { "s", 1, 1, 13, 1 },
+
+#define F_NPS_M (F_NPS_SR + 1)
+ { "m", 1, 1, 7, 1 },
+
+#define F_NPS_FLAG (F_NPS_M + 1)
{ "f", 1, 1, 20, 1 },
#define F_NPS_R (F_NPS_FLAG + 1)
@@ -1454,6 +1510,21 @@ const struct arc_flag_operand arc_flag_operands[] =
#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
{ "x4", 2, 2, 22, 1 },
+
+#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
+ { "core", 1, 3, 6, 1 },
+
+#define F_NPS_CLSR (F_NPS_CORE + 1)
+ { "clsr", 2, 3, 6, 1 },
+
+#define F_NPS_ALL (F_NPS_CLSR + 1)
+ { "all", 3, 3, 6, 1 },
+
+#define F_NPS_GIC (F_NPS_ALL + 1)
+ { "gic", 4, 3, 6, 1 },
+
+#define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
+ { "gic", 5, 3, 6, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); @@ -1519,7 +1590,7 @@ const struct arc_flag_class arc_flag_classes[] =
F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
- F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
#define C_AA_ADDR3 (C_CC + 1)
#define C_AA27 (C_CC + 1)
@@ -1583,7 +1654,13 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NPS_NA (C_NPS_CL + 1)
{ F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
-#define C_NPS_F (C_NPS_NA + 1)
+#define C_NPS_SR (C_NPS_NA + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
+
+#define C_NPS_M (C_NPS_SR + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
+
+#define C_NPS_F (C_NPS_M + 1)
{ F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
#define C_NPS_R (C_NPS_F + 1)
@@ -1645,6 +1722,21 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
{ F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
+
+#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
+ { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
+
+#define C_NPS_CLSR (C_NPS_CORE + 1)
+ { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
+
+#define C_NPS_ALL (C_NPS_CLSR + 1)
+ { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
+
+#define C_NPS_GIC (C_NPS_ALL + 1)
+ { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
+
+ #define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
+ { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
};
const unsigned char flags_none[] = { 0 }; @@ -2274,7 +2366,10 @@ const struct arc_operand arc_operands[] =
#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
{ 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
+#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
+ { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+insert_nps_size_16bit, extract_nps_size_16bit },
+
+#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
{ 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1) @@ -2283,7 +2378,13 @@ const struct arc_operand arc_operands[] = #define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
{ 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset },
-#define NPS_R_DST_3B_48 (NPS_DMA_IMM_OFFSET + 1)
+#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
+ { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
+
+#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
+ { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
+
+#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
{ 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
@@ -2414,7 +2515,8 @@ const struct arc_flag_special arc_flag_special_cases[] =
{ "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
+ F_NO_T, F_NULL } },
{ "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
--
1.7.1
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