[PATCH] RISC-V: Fix SLTI disassembly

Palmer Dabbelt palmer@dabbelt.com
Fri Jun 23 01:55:00 GMT 2017


From: Andrew Waterman <andrew@sifive.com>

2017-05-11  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
	alias; do not mark SLTI instruction as an alias.
---
 opcodes/ChangeLog   | 5 +++++
 opcodes/riscv-opc.c | 4 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b2e7729024..cd96960b8f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-11  Andrew Waterman  <andrew@sifive.com>
+
+	* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
+	alias; do not mark SLTI instruction as an alias.
+
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (RM_0FAE_REG_5): Removed.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0188a653f2..9914c44744 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -245,9 +245,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"snez",      "I",   "d,t",  MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
 {"sltz",      "I",   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
 {"sgtz",      "I",   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
-{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
+{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
 {"slt",       "I",   "d,s,t",  MATCH_SLT, MASK_SLT, match_opcode, 0 },
-{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
+{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
 {"sltiu",     "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
 {"sltu",      "I",   "d,s,t",  MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
 {"sltu",      "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },
-- 
2.13.0



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