[PATCH] x86: also correctly support opcode TEST aliases

[Jan Beulich]

Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.

opcodes/
2017-02-21  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.

--- 2017-02-21/opcodes/i386-dis.c
+++ 2017-02-21/opcodes/i386-dis.c
@@ -3511,7 +3511,7 @@ static const struct dis386 reg_table[][8
   /* REG_F6 */
   {
     { "testA",	{ Eb, Ib }, 0 },
-    { Bad_Opcode },
+    { "testA",	{ Eb, Ib }, 0 },
     { "notA",	{ Ebh1 }, 0 },
     { "negA",	{ Ebh1 }, 0 },
     { "mulA",	{ Eb }, 0 },	/* Don't print the implicit %al register,  */
@@ -3522,7 +3522,7 @@ static const struct dis386 reg_table[][8
   /* REG_F7 */
   {
     { "testQ",	{ Ev, Iv }, 0 },
-    { Bad_Opcode },
+    { "testQ",	{ Ev, Iv }, 0 },
     { "notQ",	{ Evh1 }, 0 },
     { "negQ",	{ Evh1 }, 0 },
     { "mulQ",	{ Ev }, 0 },	/* Don't print the implicit register.  */