[PATCH, RFC] Add support for choosing disassembler cpu in GDB for POWER.
Fri Oct 28 18:47:00 GMT 2016
Peter Bergner wrote:
> On 10/28/16 9:15 AM, Ulrich Weigand wrote:
> > It's probably not that important to exactly match objdump
> > behavior here. B.t.w. how do you even enter a space as
> > separator with the -M option?
> bergner@genoa:~$ objdump -d -M'power5 power6' wait.o | grep warning
> warning: ignoring unknown -Mpower5 power6 option
OK, well :-) As I said, it's probably not important to
exactly match *this* detail in the GDB command ...
> But not all arches have descriptions paired with the option name.
> Looking at Pedro's objdump output from before:
> The following ARM specific disassembler options are supported for use with
> the -M switch:
> reg-names-special-atpcs Select special register names used in the ATPCS
> reg-names-atpcs Select register names used in the ATPCS
> reg-names-apcs Select register names used in the APCS
> reg-names-std Select register names used in ARM's ISA documentation
> reg-names-gcc Select register names used by GCC
> reg-names-raw Select raw register names
> force-thumb Assume all insns are Thumb insns
> no-force-thumb Examine preceding label to determine an insn's type
> This would work well for what you propose, but on power, we just dump them out:
> The following PPC specific disassembler options are supported for use with
> the -M switch:
> 403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455,
> 750cl, 821, 850, 860, a2, altivec, any, booke, booke32, cell, com,
> e200z4, e300, e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, power4,
> power5, power6, power7, power8, power9, ppc, ppc32, ppc64, ppc64bridge,
> ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx,
> spe, titan, vle, vsx, htm, 32, 64
Hmm, I see. I guess we could have NULL description string for those,
and then the common printing routine could choose the compact output ...
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
More information about the Binutils