[committed] MIPS/BFD: Correct register index calculation in BZ16_REG

[Maciej W. Rozycki]

For the 3-bit register encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } return
the 5-bit encodings of { 16, 17, 2, 3, 4, 5, 6, 7 } respectively rather
than { 24, 25, 2, 3, 4, 5, 6, 7 }.

	bfd/
	* elfxx-mips.c (BZ16_REG): Correct calculation.
---
Tristan,

 OK for 2.26?

  Maciej

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 4ece819..176970a 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -13110,7 +13110,7 @@ static const struct opcode_descriptor bz_insns_16[] = {
 
 /* Switch between a 5-bit register index and its 3-bit shorthand.  */
 
-#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0x17) + 2)
+#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2)
 #define BZ16_REG_FIELD(r) \
   (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)