[OPCODES][ARM]Fix mask for a few coprocessor opcodes.

[Renlin Li]

Hi all,

This is a simple patch to fix a few coprocessor opcode masks.
for example:

.inst 0xfe011a10 //unpredictable mcr2 instruction.
.inst 0xfe011a00 // valid vsel.

However, when objdumped, those two all dumped as:

0:	fe011a10 	vseleq.f32	s2, s2, s0
4:	fe011a00 	vseleq.f32	s2, s2, s0

This is not correct. The correct dump should be:

0:	fe011a10 	mcr2	10, 0, r1, cr1, cr0, {0}	; <UNPREDICTABLE>
4:	fe011a00 	vseleq.f32	s2, s2, s0


The mask here is not strict enough to differentiate is from other instructions.
I discovered this when you were adding support for armv8.2.

This patch depends on another patch post earlier to give the unpredictable
information about mcr2 instruction:

https://sourceware.org/ml/binutils/2016-02/msg00261.html

All Binutils regression tests run Okay without any new issues. Okay to commit?



opcodes/ChangeLog:

2016-02-18  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
	vrint(mpna).
	* testsuite/gas/arm/mask_1.d: New.
	* testsuite/gas/arm/mask_1.s: New.

-------------- next part --------------
A non-text attachment was scrubbed...
Name: mask.diff
Type: text/x-patch
Size: 4941 bytes
Desc: not available
URL: <https://sourceware.org/pipermail/binutils/attachments/20160218/704f4ce1/attachment.bin>