[AArch64][SVE 16/32] Use specific insert/extract methods for fpimm

[Richard Sandiford]

FPIMM used the normal "imm" insert/extract methods, with a specific
test for FPIMM in the extract method.  SVE needs to use the same
extractors, so rather than add extra checks for specific operand types,
it seemed cleaner to use a separate insert/extract method.

OK to install?

Thanks,
Richard


opcodes/
	* aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
	for FPIMM.
	* aarch64-asm.h (ins_fpimm): New inserter.
	* aarch64-asm.c (aarch64_ins_fpimm): New function.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_fpimm): New extractor.
	* aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
	(aarch64_ext_fpimm): New function.
	* aarch64-dis-2.c: Regenerate.

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 605bf08..439dd3d 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -500,7 +500,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 34:
       return aarch64_ins_ldst_elemlist (self, info, code, inst);
     case 37:
-    case 46:
     case 47:
     case 48:
     case 49:
@@ -525,6 +524,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 41:
     case 42:
       return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
+    case 46:
+      return aarch64_ins_fpimm (self, info, code, inst);
     case 59:
       return aarch64_ins_limm (self, info, code, inst);
     case 60:
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 3b0a383..f291495 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -417,6 +417,16 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return NULL;
 }
 
+/* Insert fields for an 8-bit floating-point immediate.  */
+const char *
+aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
+		   aarch64_insn *code,
+		   const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  insert_all_fields (self, code, info->imm.value);
+  return NULL;
+}
+
 /* Insert #<fbits> for the immediate operand in fp fix-point instructions,
    e.g.  SCVTF <Dd>, <Wn>, #<fbits>.  */
 const char *
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index ad9183d..3211aff 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -50,6 +50,7 @@ AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
 AARCH64_DECL_OPD_INSERTER (ins_imm);
 AARCH64_DECL_OPD_INSERTER (ins_imm_half);
 AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
+AARCH64_DECL_OPD_INSERTER (ins_fpimm);
 AARCH64_DECL_OPD_INSERTER (ins_fbits);
 AARCH64_DECL_OPD_INSERTER (ins_aimm);
 AARCH64_DECL_OPD_INSERTER (ins_limm);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 8e85dbf..a86a84d 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10450,7 +10450,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 34:
       return aarch64_ext_ldst_elemlist (self, info, code, inst);
     case 37:
-    case 46:
     case 47:
     case 48:
     case 49:
@@ -10478,6 +10477,8 @@ aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
     case 43:
       return aarch64_ext_shll_imm (self, info, code, inst);
+    case 46:
+      return aarch64_ext_fpimm (self, info, code, inst);
     case 59:
       return aarch64_ext_limm (self, info, code, inst);
     case 60:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 67daa66..4c3b521 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -598,9 +598,6 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
 
   imm = extract_all_fields (self, code);
 
-  if (info->type == AARCH64_OPND_FPIMM)
-    info->imm.is_fp = 1;
-
   if (operand_need_sign_extension (self))
     imm = sign_extend (imm, get_operand_fields_width (self) - 1);
 
@@ -695,6 +692,17 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return 1;
 }
 
+/* Decode an 8-bit floating-point immediate.  */
+int
+aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
+		   const aarch64_insn code,
+		   const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  info->imm.value = extract_all_fields (self, code);
+  info->imm.is_fp = 1;
+  return 1;
+}
+
 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>.  */
 int
 aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 9be5d7f..1f10157 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -72,6 +72,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_shll_imm);
 AARCH64_DECL_OPD_EXTRACTOR (ext_imm);
 AARCH64_DECL_OPD_EXTRACTOR (ext_imm_half);
 AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_modified);
+AARCH64_DECL_OPD_EXTRACTOR (ext_fpimm);
 AARCH64_DECL_OPD_EXTRACTOR (ext_fbits);
 AARCH64_DECL_OPD_EXTRACTOR (ext_aimm);
 AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index b82678f..9a831e4 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2738,7 +2738,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
       "an immediate shift amount of 8, 16 or 32")			\
     X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0")				\
     X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0")				\
-    Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8),				\
+    Y(IMMEDIATE, fpimm, "FPIMM", 0, F(FLD_imm8),			\
       "an 8-bit floating-point constant")				\
     Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr),				\
       "the right rotate amount")					\