[MSP430-elf] Linking issue
Orlando Arias
orlandoarias@gmail.com
Mon Sep 28 20:31:00 GMT 2015
Greetings,
I am currently experiencing an issue when linking programs for the
msp430-elf target. The linker complains that some symbols are being
redefined. It does generate a working binary but I am not sure where the
warnings are being generated. I thought I would ask here before opening
a bug report.
The tools I am currently using:
msp430-elf-binutils 2.25.1 with this patch:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=0f8f0c57ea4742ad2d9b0598a18243331c1c06e3
msp430-elf-gcc 5.2.0
[stock]
msp430-elf-mcu 3.5.0.0
TI's latest linker scripts, modified as per:
https://sourceware.org/bugzilla/show_bug.cgi?id=17940
msp430-elf-newlib 2.2.0.20150824
September snapshot fails to compile, modified nosys.specs file as to
remove duplicate definition error [will report this in the proper
mailing list].
The warnings in question:
/usr/bin/msp430-elf-ld:msp430f2013.ld:41: warning: redeclaration of
memory region `SFR'
/usr/bin/msp430-elf-ld:msp430f2013.ld:42: warning: redeclaration of
memory region `PERIPHERAL_8BIT'
/usr/bin/msp430-elf-ld:msp430f2013.ld:43: warning: redeclaration of
memory region `PERIPHERAL_16BIT'
/usr/bin/msp430-elf-ld:msp430f2013.ld:44: warning: redeclaration of
memory region `RAM'
/usr/bin/msp430-elf-ld:msp430f2013.ld:45: warning: redeclaration of
memory region `INFOMEM'
/usr/bin/msp430-elf-ld:msp430f2013.ld:46: warning: redeclaration of
memory region `INFOA'
/usr/bin/msp430-elf-ld:msp430f2013.ld:47: warning: redeclaration of
memory region `INFOB'
/usr/bin/msp430-elf-ld:msp430f2013.ld:48: warning: redeclaration of
memory region `INFOC'
/usr/bin/msp430-elf-ld:msp430f2013.ld:49: warning: redeclaration of
memory region `INFOD'
/usr/bin/msp430-elf-ld:msp430f2013.ld:50: warning: redeclaration of
memory region `ROM'
/usr/bin/msp430-elf-ld:msp430f2013.ld:51: warning: redeclaration of
memory region `VECT1'
/usr/bin/msp430-elf-ld:msp430f2013.ld:52: warning: redeclaration of
memory region `VECT2'
/usr/bin/msp430-elf-ld:msp430f2013.ld:53: warning: redeclaration of
memory region `VECT3'
/usr/bin/msp430-elf-ld:msp430f2013.ld:54: warning: redeclaration of
memory region `VECT4'
/usr/bin/msp430-elf-ld:msp430f2013.ld:55: warning: redeclaration of
memory region `VECT5'
/usr/bin/msp430-elf-ld:msp430f2013.ld:56: warning: redeclaration of
memory region `VECT6'
/usr/bin/msp430-elf-ld:msp430f2013.ld:57: warning: redeclaration of
memory region `VECT7'
/usr/bin/msp430-elf-ld:msp430f2013.ld:58: warning: redeclaration of
memory region `VECT8'
/usr/bin/msp430-elf-ld:msp430f2013.ld:59: warning: redeclaration of
memory region `VECT9'
/usr/bin/msp430-elf-ld:msp430f2013.ld:60: warning: redeclaration of
memory region `VECT10'
/usr/bin/msp430-elf-ld:msp430f2013.ld:61: warning: redeclaration of
memory region `VECT11'
/usr/bin/msp430-elf-ld:msp430f2013.ld:62: warning: redeclaration of
memory region `VECT12'
/usr/bin/msp430-elf-ld:msp430f2013.ld:63: warning: redeclaration of
memory region `VECT13'
/usr/bin/msp430-elf-ld:msp430f2013.ld:64: warning: redeclaration of
memory region `VECT14'
/usr/bin/msp430-elf-ld:msp430f2013.ld:65: warning: redeclaration of
memory region `VECT15'
/usr/bin/msp430-elf-ld:msp430f2013.ld:66: warning: redeclaration of
memory region `RESETVEC'
Attached you will find the Makefile, source code and linker script in
question. Any suggestions as where to look are greatly appreciated.
Thank you.
Cheers,
Orlando.
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# MSP430 Makefile
# Change to your system's configuration
# Microcontroller
MMCU = msp430f2013
PROG = uif
ELF = blink.elf
SRC = $(wildcard *.c)
OBJ = $(SRC:.c=.o)
CC = msp430-elf-gcc
LD = msp430-elf-gcc
SIZE = msp430-elf-size
STRIP = msp430-elf-strip
CFLAGS := -mmcu=$(MMCU) -Os -Wall -pedantic -fdata-sections -ffunction-sections
LDFLAGS := -mmcu=$(MMCU) -fdata-sections -ffunction-sections
LDFLAGS += $(LDFLAGS) --specs=nosys.specs #-Wl,--gc-sections -Wl,--strip-all
all: $(ELF) size
debug: CFLAGS += -DDEBUG -g
debug: all
$(ELF): $(OBJ)
@echo -e "\033[36;1mLinking... \033[0m$(ELF)"
@$(LD) -o $(ELF) $(OBJ) $(LDFLAGS)
prog: $(ELF)
@mspdebug $(PROG) "prog $(ELF)"
%.o:%.c
@echo -e "\033[34;1mCompiling... \033[0m$<"
@$(CC) -c $(CFLAGS) $< -o $@
clean:
@-rm -f $(ELF) $(OBJ)
size: $(ELF)
@$(SIZE) $(ELF)
strip:
@$(STRIP) $(ELF)
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/* ============================================================================ */
/* Copyright (c) 2015, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/* This file supports MSP430F2013 devices. */
/* Version: 1.173 */
/* Default linker script, for normal executables */
OUTPUT_ARCH(msp430)
ENTRY(_start)
MEMORY {
SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */
PERIPHERAL_8BIT : ORIGIN = 0x0010, LENGTH = 0x00F0 /* END=0x0100, size 240 */
PERIPHERAL_16BIT : ORIGIN = 0x0100, LENGTH = 0x0100 /* END=0x0200, size 256 */
RAM : ORIGIN = 0x0200, LENGTH = 0x0080 /* END=0x027F, size 128 */
INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 4 64-byte segments */
INFOA : ORIGIN = 0x10C0, LENGTH = 0x0040 /* END=0x10FF, size 64 */
INFOB : ORIGIN = 0x1080, LENGTH = 0x0040 /* END=0x10BF, size 64 */
INFOC : ORIGIN = 0x1040, LENGTH = 0x0040 /* END=0x107F, size 64 */
INFOD : ORIGIN = 0x1000, LENGTH = 0x0040 /* END=0x103F, size 64 */
ROM (rx) : ORIGIN = 0xF800, LENGTH = 0x07E0 /* END=0xFFDF, size 2016 */
VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002
VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002
VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002
VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002
VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002
VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002
VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002
VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002
VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002
VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002
VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002
VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002
VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002
VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002
VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002
RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
}
SECTIONS
{
__interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1
__interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2
__interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_port1)) } > VECT3
__interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_port2)) } > VECT4
__interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) KEEP (*(__interrupt_vector_usi)) } > VECT5
__interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_sd16)) } > VECT6
__interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7
__interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8
__interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_timera1)) } > VECT9
__interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_timera0)) } > VECT10
__interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11
__interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12
__interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13
__interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14
__interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15
__reset_vector :
{
KEEP (*(__interrupt_vector_16))
KEEP (*(__interrupt_vector_reset))
KEEP (*(.resetvec))
} > RESETVEC
.rodata : {
. = ALIGN(2);
*(.plt)
*(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
*(.rodata1)
*(.eh_frame_hdr)
KEEP (*(.eh_frame))
KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
PROVIDE (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE (__fini_array_end = .);
LONG(0); /* Sentinel. */
/* gcc uses crtbegin.o to find the start of the constructors, so
we make sure it is first. Because this is a wildcard, it
doesn't matter if the user does not actually link against
crtbegin.o; the linker won't look for a file to match a
wildcard. The wildcard also means that it doesn't matter which
directory crtbegin.o is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from from the
crtend.o file until after the sorted ctors. The .ctor section
from the crtend file contains the end of ctors marker and it
must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} > ROM
.text :
{
. = ALIGN(2);
PROVIDE (_start = .);
KEEP (*(SORT(.crt_*)))
*(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.interp .hash .dynsym .dynstr .gnu.version*)
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(2);
KEEP (*(.init))
KEEP (*(.fini))
KEEP (*(.tm_clone_table))
} > ROM
.data : {
. = ALIGN(2);
PROVIDE (__datastart = .);
KEEP (*(.jcr))
*(.data.rel.ro.local) *(.data.rel.ro*)
*(.dynamic)
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
*(.data1)
*(.got.plt) *(.got)
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
. = ALIGN(2);
*(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
. = ALIGN(2);
_edata = .;
PROVIDE (edata = .);
PROVIDE (__dataend = .);
} > RAM AT>ROM
/* Note that crt0 assumes this is a multiple of two; all the
start/stop symbols are also assumed word-aligned. */
PROVIDE(__romdatastart = LOADADDR(.data));
PROVIDE (__romdatacopysize = SIZEOF(.data));
.bss : {
. = ALIGN(2);
PROVIDE (__bssstart = .);
*(.dynbss)
*(.sbss .sbss.*)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN(2);
*(COMMON)
PROVIDE (__bssend = .);
} > RAM
PROVIDE (__bsssize = SIZEOF(.bss));
.noinit (NOLOAD) : {
. = ALIGN(2);
PROVIDE (__noinit_start = .);
*(.noinit)
. = ALIGN(2);
PROVIDE (__noinit_end = .);
end = .;
} > RAM
.stack (ORIGIN (RAM) + LENGTH(RAM)) :
{
PROVIDE (__stack = .);
*(.stack)
}
.infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
.infoB : {} > INFOB
.infoC : {} > INFOC
.infoD : {} > INFOD
.MP430.attributes 0 :
{
KEEP (*(.MSP430.attributes))
KEEP (*(.gnu.attributes))
KEEP (*(__TI_build_attributes))
}
/* The rest are all not normally part of the runtime image. */
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/DISCARD/ : { *(.note.GNU-stack) }
}
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