[binutils][2.24][objdump][ARM] Backport fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp
Richard Earnshaw
Richard.Earnshaw@foss.arm.com
Tue Sep 15 10:23:00 GMT 2015
On 10/09/15 15:24, Andre Vieira wrote:
> NOPS with invalid SBO/SBZ fields were being wrongfully translated to TEQ's.
> The 26-bit versions of TEQ/TST/CMN/CMP are now marked UNPREDICTABLE for
> ARM V6 and higher.
> See the definition of UNPREDICTABLE instructions and instruction
> definitions for TEQ/TST/CMN/CMP in the ARM Architecture Reference Manual
> ARMv7-A and ARMv7-R edition, reference ARM DDI0406C,
> on infocenter.arm.com.
>
> This patch backports the fix from trunk to the binutils 2.24 branch.
>
> The original patch is at:
> https://sourceware.org/ml/binutils/2015-08/msg00028.html
>
>
Why does this need to be backported? It doesn't feel like a regression
to me.
R.
> opcodes/ChangeLog:
>
> 2015-07-09 Andre Vieira <andre.simoesdiasvieira@arm.com>
>
> Backport from mainline
> 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
>
> * arm-dis.c (print_insn_arm): Disassembling for all targets V6
> and higher with ARM instruction set will now mark the 26-bit
> versions of teq,tst,cmn and cmp as UNPREDICTABLE.
> (arm_opcodes): Fix for unpredictable nop being recognized as a
> teq.
>
> gas/testsuite/ChangeLog:
>
> 2015-07-09 Andre Vieira <andre.simoesdiasvieira@arm.com>
>
> Backport from mainline
> 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
>
> * gas/arm/nops.d: New.
> * gas/arm/nops.s: New.
> * gas/arm/inst.d: Changed expectation file for 26-bit teq,
> tst, cmn and cmp.
>
> 0001-backport-for-fix-unpredictable.patch
>
>
> From f7495465d7d55e2971263427ad920b0c5c96e458 Mon Sep 17 00:00:00 2001
> From: Andre Simoes Dias Vieira <andsim01@arm.com>
> Date: Mon, 7 Sep 2015 12:45:04 +0100
> Subject: [PATCH] Backport for fix unpredictable nops and 24-bit version of
> teq,tst,cmp,cmn instructions
>
> ---
> gas/testsuite/gas/arm/inst.d | 32 ++++++++++++++++----------------
> gas/testsuite/gas/arm/nops.d | 11 +++++++++++
> gas/testsuite/gas/arm/nops.s | 4 ++++
> opcodes/arm-dis.c | 10 +++++++---
> 4 files changed, 38 insertions(+), 19 deletions(-)
> create mode 100644 gas/testsuite/gas/arm/nops.d
> create mode 100644 gas/testsuite/gas/arm/nops.s
>
> diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d
> index e298c5fe41b401dcdb3d4ef87da1bdf58786b480..d7ca4a3ce849980a7524c5875a74ca436727993c 100644
> --- a/gas/testsuite/gas/arm/inst.d
> +++ b/gas/testsuite/gas/arm/inst.d
> @@ -95,22 +95,22 @@ Disassembly of section .text:
> 0+14c <[^>]*> e1720004 ? cmn r2, r4
> 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5
> 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1
> -0+158 <[^>]*> e330f00a ? teq r0, #10
> -0+15c <[^>]*> e132f004 ? teq r2, r4
> -0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5
> -0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1
> -0+168 <[^>]*> e370f00a ? cmn r0, #10
> -0+16c <[^>]*> e172f004 ? cmn r2, r4
> -0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5
> -0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1
> -0+178 <[^>]*> e350f00a ? cmp r0, #10
> -0+17c <[^>]*> e152f004 ? cmp r2, r4
> -0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5
> -0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1
> -0+188 <[^>]*> e310f00a ? tst r0, #10
> -0+18c <[^>]*> e112f004 ? tst r2, r4
> -0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5
> -0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1
> +0+158 <[^>]*> e330f00a ? teq r0, #10 ; <UNPREDICTABLE>
> +0+15c <[^>]*> e132f004 ? teq r2, r4 ; <UNPREDICTABLE>
> +0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 ; <UNPREDICTABLE>
> +0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 ; <UNPREDICTABLE>
> +0+168 <[^>]*> e370f00a ? cmn r0, #10 ; <UNPREDICTABLE>
> +0+16c <[^>]*> e172f004 ? cmn r2, r4 ; <UNPREDICTABLE>
> +0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 ; <UNPREDICTABLE>
> +0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 ; <UNPREDICTABLE>
> +0+178 <[^>]*> e350f00a ? cmp r0, #10 ; <UNPREDICTABLE>
> +0+17c <[^>]*> e152f004 ? cmp r2, r4 ; <UNPREDICTABLE>
> +0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 ; <UNPREDICTABLE>
> +0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 ; <UNPREDICTABLE>
> +0+188 <[^>]*> e310f00a ? tst r0, #10 ; <UNPREDICTABLE>
> +0+18c <[^>]*> e112f004 ? tst r2, r4 ; <UNPREDICTABLE>
> +0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 ; <UNPREDICTABLE>
> +0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 ; <UNPREDICTABLE>
> 0+198 <[^>]*> e0000291 ? mul r0, r1, r2
> 0+19c <[^>]*> e0110392 ? muls r1, r2, r3
> 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0
> diff --git a/gas/testsuite/gas/arm/nops.d b/gas/testsuite/gas/arm/nops.d
> new file mode 100644
> index 0000000000000000000000000000000000000000..54ed13ab75ce576f9c08e07bab11c38db68ce88d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/nops.d
> @@ -0,0 +1,11 @@
> +# name: NOP<c> instructions
> +# objdump: -dr --prefix-addresses --show-raw-insn
> +
> +.*: +file format .*arm.*
> +
> +Disassembly of section \.text:
> +0+000 <[^>]*> 0320f000 ? nopeq \{0\}
> +0+004 <[^>]*> 7320f000 ? nopvc \{0\}
> +0+008 <[^>]*> 7320d700 ? nopvc \{0\} ; <UNPREDICTABLE>
> +
> +
> diff --git a/gas/testsuite/gas/arm/nops.s b/gas/testsuite/gas/arm/nops.s
> new file mode 100644
> index 0000000000000000000000000000000000000000..704c10b66d2e25f9748c7eca13bf38193c83d35b
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/nops.s
> @@ -0,0 +1,4 @@
> +.arm
> +.inst 0x0320f000
> +.inst 0x7320f000
> +.inst 0x7320d700
> diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
> index 18a553bd2be7b7fdc09918ce25c0cc985ba28cbe..13fe26d263ffc754a00de85eb825e81d34fcd692 100644
> --- a/opcodes/arm-dis.c
> +++ b/opcodes/arm-dis.c
> @@ -1187,9 +1187,9 @@ static const struct opcode32 arm_opcodes[] =
> {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
> {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
>
> - {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
> - {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
> - {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
> + {ARM_EXT_V1, 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
> + {ARM_EXT_V1, 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
> + {ARM_EXT_V1, 0x01300010, 0x0ff00090, "teq%p%c\t%16-19R, %o"},
>
> {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
> {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
> @@ -1270,6 +1270,7 @@ static const struct opcode32 arm_opcodes[] =
> {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
> {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
>
> + {ARM_EXT_V1, 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
> /* The rest. */
> {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
> {0, 0x00000000, 0x00000000, 0}
> @@ -1515,6 +1516,7 @@ static const struct opcode32 thumb32_opcodes[] =
> {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
> {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
> {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
> + {ARM_EXT_V7, 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
> {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
> {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
>
> @@ -3371,6 +3373,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
> obsolete in V6 onwards. */
> if ((private_data->features.core & ARM_EXT_V6) == 0)
> func (stream, "p");
> + else
> + is_unpredictable = TRUE;
> }
> break;
>
>
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