[13/16][binutils][AARCH64]Add relocation support for large memory model. [BFD]Add TLSGD relaxation support

[Renlin Li]

Hi all,

This patch adds TLSGD relaxation support into bfd linker. According the 
documentation, the following two relaxations can be done under different 
conditions.

Here is the TLSGD access sequence under large memory:

movz a0, #:tlsgd_g1:x             R_AARCH64_TLSGD_MOVW_G1
movk a0, #:tlsgd_g0:x             R_AARCH64_TLSGD_MOVW_G0_NC
add  a0, gp, a0
bl   __tls_get_addr                    R_AARCH64_CALL26
nop

It can be relaxed into following TLSLE code sequence :

movz a0, #:tprel_g2:x                  R_AARCH64_TLSLE_MOVW_TPREL_G2
movk a0, #:tprel_g1_nc:x R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
movk a0, #:tprel_g0_nc:x R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
mrs  a1, tpidr_el0
add  a0, a0, a1

Or into TLSIE code sequence:

movz a0, #:gottprel_g1:x R_AARCH64_TLSIE_MOVW_GOTTPREL_G1
movk a0, #:gottprel_g0_nc:x R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
ldr  a0, [gp, a0]
mrs  a1, tpidr_el0
add  a0, a0, a1

Binutils and linker checked Okay, Okay to commit?

Regards,
Renlin Li

bfd/ChangeLog:

2015-09-08  Renlin Li <renlin.li@arm.com>

     * elfnn-aarch64.c(IS_AARCH64_TLS_RELAX_RELOC):
     Add relaxation support for TLSGD_MOVW_G0_NC and TLSGD_MOVW_G1.
     (aarch64_tls_transition_without_check): Likewise
     (elfNN_aarch64_tls_relax): Likwise.

ld/testsuite/ChangeLog:


2015-09-08  Renlin Li <renlin.li@arm.com>

     * ld-aarch64/aarch64-elf.exp: run new test
     * ld-aarch64/tls-relax-large-gd-ie.d: New.
     * ld-aarch64/tls-relax-large-gd-ie.s: New.
     * ld-aarch64/tls-relax-large-gd-le.d: New.
     * ld-aarch64/tls-relax-large-gd-le.s: New.
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