[committed, PATCH] PR binutis/18386: callw with 0x66 prefix incorrectly disassembled in 64-bit mode

[H.J. Lu]

On Mon, May 11, 2015 at 6:22 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 11.05.15 at 14:40, <hjl.tools@gmail.com> wrote:
>> On Mon, May 11, 2015 at 4:29 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 11.05.15 at 13:04, <hjl.tools@gmail.com> wrote:
>>>> On Mon, May 11, 2015 at 12:28 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>>> On 09.05.15 at 15:52, <hjl.tools@gmail.com> wrote:
>>>>>> The operand size prefix (0x66) is ignored for 32-bit PC-relative call,
>>>>>> jmp and jcc in 64-bit mode.
>>>>>
>>>>> Now that's again a change that should have been discussed
>>>>> before committing: While it is correct for the Intel implementation
>>>>> of x86-64, it isn't for AMD's original (and I'd tend to say that the
>>>>> latter is more correct, since afaik there's nowhere that exceptions
>>>>> are being made for the meaning of the operand size prefix).
>>>>
>>>> It is also correct for AMD.
>>>
>>> Very certainly not, based on practical observation: This code
>>>
>>> x86_64:
>>>         mov     rcx, rsp
>>>         .byte 0x66, 0xe8, 0x00, 0x00, 0x90, 0x90
>>>         xchg    rcx, rsp
>>>         ret
>>>
>>> yields
>>>
>>> Reading symbols from /home/jbeulich/x86-64...done.
>>> (gdb) break x86_64
>>> Breakpoint 1 at 0x400520
>>> (gdb) r
>>> Starting program: /home/jbeulich/x86-64
>>> Failed to read a valid object file image from memory.
>>>
>>> Breakpoint 1, 0x0000000000400520 in x86_64 ()
>>> (gdb) x/5i $pc
>>> => 0x400520 <x86_64>:   mov    rcx,rsp
>>>    0x400523 <x86_64+3>: call   0x527
>>>    0x400527 <x86_64+7>: nop
>>>    0x400528 <x86_64+8>: nop
>>>    0x400529 <x86_64+9>: xchg   rcx,rsp
>>> (gdb) c
>>> Continuing.
>>>
>>> Program received signal SIGSEGV, Segmentation fault.
>>> 0x0000000000000527 in ?? ()
>>>
>>> with RSP also decremented by just 2.
>>>
>>
>> The displacement is still 32-bit, but stack adjustment is
>
> No, it's not - as you can see from the SEGV happing on address
> 00000527. If the displacement was 32 bits, then the faulting
> address would have been 90900527.
>
>> different.  Display it as callq isn't accurate for AMD and
>> callw is not correct for both AMD and Intel.  I will leave it
>> as is since I don't think we should add another instruction
>> for this.
>>

So AMD and Intel are different.  I think

data16 callq rel32

is better than

callw rel16
foobar



-- 
H.J.