[PATCH] add znver1 processor.

[Gopalasubramanian, Ganesh]

> Is there _any_ public documentation available for this new processor model?

As of now, no!
We are pulling in efforts to make this publicly available soon.

-Ganesh

-----Original Message-----
From: Jan Beulich [mailto:JBeulich@suse.com] 
Sent: Thursday, March 19, 2015 3:34 PM
To: Gopalasubramanian, Ganesh
Cc: H.J. Lu (hjl.tools@gmail.com); binutils@sourceware.org
Subject: Re: [PATCH] add znver1 processor.

>>> On 10.03.15 at 08:49, <Ganesh.Gopalasubramanian@amd.com> wrote:
> Attached patch adds the following.
> 	* New AMD znver1 processor. The architecture has the below features
> 		* TBM, FMA4, XOP, LWP: ISAs are not supported.
> 		* SMAP, RDSEED, SHA, XSAVEC, XSAVES, CLFLUSHOPT, ADCX: ISAs are supported.
> 	* New CLZERO instruction support. 
> 		* clzero has opcode "0F 01 FC".
> 		* clzero gets enabled with CPUID, 8000_0008, EBX[0] =1.
> 		* clzero instruction zero's out the 64 byte cache line specified in rax. 
> Bits 5:0 of rAX are ignored