[Patch:RL78]: Objdump utility generates incorrect disassembler output for SFR registers.

[Vinay Kumar. G]

Hi,
In GNURL78 toolchain SFR registers are not visible in the disassembly 
generated by objdump utility.

Below testcase is for 'psw' and 'sp' registers. Same behavior is observed 
with SPL, SPH, CS, ES, PMC and MEM  sfr registers.

For example:
/*test.s*/
.text
.set sfr, 0xffff8
	mov     a, sfr
	mov     sfr, a
	mov     sfr, #123
	xch     a, sfr
.set sfrp, 0xffff8
	movw    ax, sfrp
	movw    sfrp, ax
	movw    sfrp, #0x1234
	
$rl78-elf-as test.s -o test.o -aln=test.lst
$rl78-elf-objdump -d test.o

Disassembly of section .text:

00000000 <.text>:
   0:   8e fa     	 mov     a, psw
   2:   9e fa        mov     0xffffa, a  ---> expected "mov psw, a"
   4:   ce fa 7b     mov     psw, #123
   7:   61 ab fa     xch     a, 0xffffa  ---> expected "xch a, psw"
   a:   ae f8        movw    ax, sp
   c:   be f8        movw    sp, ax
   e:   cb f8 34 12  movw    0xffff8, #0x1234 ---> expected "movw  sp, #0x1234"

Please review below patch and commit the same if OK.

Best Regards,
Vinay

/*******************************************************************/
opcodes/ChangeLog
2015-07-07  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc : Updated to display sfr register names.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c : Updated to display sfr register names.
	
--- opcodes/rl78-decode.opc.org	2015-07-06 14:34:35.446054908 +0530
+++ opcodes/rl78-decode.opc	2015-06-29 17:37:15.180773129 +0530
@@ -775,7 +775,7 @@
 	break;
       }
 
-/** 1001 1110			mov	%0, %1				*/
+/** 1001 1110			mov	%s0, %1				*/
   ID(mov); DM(None, SFR); SR(A);
 
 /*----------------------------------------------------------------------*/
@@ -893,7 +893,7 @@
 /** 1011 1101			movw	%0, %1				*/
   ID(mov); W(); DM(None, SADDR); SR(AX);
 
-/** 1100 1011			movw	%0, #%1				*/
+/** 1100 1011			movw	%s0, #%1				*/
   ID(mov); W(); DM(None, SFR); SC(IMMU(2));
 
 /** 1011 1110			movw	%s0, %1				*/
@@ -1226,7 +1226,7 @@
 /** 0110 0001 1010 1000	       	xch	%0, %1				*/
   ID(xch); DR(A); SM(None, SADDR);
 
-/** 0110 0001 1010 1011	       	xch	%0, %1				*/
+/** 0110 0001 1010 1011	       	xch	%0, %s1				*/
   ID(xch); DR(A); SM(None, SFR);
 
 /** 0000 1000			xch	a, x				*/
--- opcodes/rl78-dis.c.orig	2015-07-06 14:20:25.192047872 +0530
+++ opcodes/rl78-dis.c	2015-07-06 14:21:51.310048585 +0530
@@ -263,6 +263,18 @@
 		      PR (PS, "psw");
 		    else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
 		      PR (PS, "sp");
+                    else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Byte)
+                      PR (PS, "spl");
+                    else if (oper->addend == 0xffff9 && do_sfr && opcode.size == RL78_Byte)
+                      PR (PS, "sph");
+                    else if (oper->addend == 0xffffc && do_sfr && opcode.size == RL78_Byte)
+                      PR (PS, "cs");
+                    else if (oper->addend == 0xffffd && do_sfr && opcode.size == RL78_Byte)
+                      PR (PS, "es");
+                    else if (oper->addend == 0xffffe && do_sfr && opcode.size == RL78_Byte)
+                      PR (PS, "pmc");
+                    else if (oper->addend == 0xfffff && do_sfr && opcode.size == RL78_Byte)
+                      PR (PS, "mem");
 		    else if (oper->addend >= 0xffe20)
 		      PR (PS, "%#x", oper->addend);
 		    else