[RL78]: Objdump does not insert space between two operands in disassembly view.

[Vinay Kumar. G]

Hi,
The RL78 toolchain "objdump" utility does not insert space between two operands 
in index addressing mode for "mov" operation. 
For example:
/* test.s  */
.text
mov     [sp+byte],a
mov     [de],a
mov     [hl],a
.end

Commands:
$rl78-elf-gcc -c -x assembler-with-cpp test.s -o test.o 
$rl78-elf-objdump -d test.o

Generated output:
test1.o:     file format elf32-rl78
Disassembly of section .text:
00000000 <.text>:
0:   98 00         mov     [sp], a
2:   99            mov     [de],a <--- expected "mov     [de], a"
3:   9b            mov     [hl],a <--- expected "mov     [hl], a"

The below patch adds a space between the two operands. New output would be as follows.
Disassembly of section .text:
00000000 <.text>:
0:   98 00         mov     [sp], a
2:   99            mov     [de], a  -> (space generated here)
3:   9b            mov     [hl], a  -> (space generated here)

Please review below patch and commit the same if OK.
Best Regards,
Vinay

/*********************************************************************/
opcodes/ChangeLog

2015-01-21  Vinay  <Vinay.G@kpit.com>

            * rl78-decode.opc (MOV): Added space between two operands for 'mov' 
              instruction in index addressing mode.
            * rl78-decode.c: Regenerate.

--- opcodes/rl78-decode.opc.org 2015-01-19 15:41:43.118023154 +0500
+++ opcodes/rl78-decode.opc     2015-01-19 15:41:59.927023203 +0500
@@ -610,7 +610,7 @@
/** 1001 1111                           mov      %e!0, %1                                   */
   ID(mov); DM(None, IMMU(2)); SR(A);

-/** 1001 1001                           mov      %e0,%1                          */
+/** 1001 1001                          mov      %e0, %1                         */
   ID(mov); DM(DE, 0); SR(A);

 /** 1100 1010                           mov      %e0, #%1                                   */
@@ -619,7 +619,7 @@
/** 1001 1010                           mov      %e0, %1                         */
   ID(mov); DM(DE, IMMU(1)); SR(A);

-/** 1001 1011                           mov      %e0,%1                          */
+/** 1001 1011                          mov      %e0, %1                         */
   ID(mov); DM(HL, 0); SR(A);

 /** 0110 0001 1101 1001                       mov      %e0, %1                                     */