[PATCH 1/2] Fix the aarch64 gas argument checking for 'fmov'

[Ralph Campbell]

Without this patch, the assembler did not generate any error messages for
the line "fmov s0, xzr" and instead generated an illegal instruction in
the binary file. With the patch, only matching size arguments are allowed
such as "fmov s0, wzr".
---
 opcodes/aarch64-tbl.h |   18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 315fdf5..d3888ae 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -279,6 +279,20 @@
   QLF2(X,S_S),			\
 }
 
+/* e.g. FMOV <Sd>, <Wn>.  */
+#define QL_MINT2FP		\
+{				\
+  QLF2(S_S,W),			\
+  QLF2(S_D,X),			\
+}
+
+/* e.g. FMOV <Xd>, <Dn>.  */
+#define QL_MFP2INT		\
+{				\
+  QLF2(W,S_S),			\
+  QLF2(X,S_D),			\
+}
+
 /* e.g. FMOV <Xd>, <Vn>.D[1].  */
 #define QL_XVD1			\
 {				\
@@ -1883,8 +1897,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
   {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
   {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
-  {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
-  {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
+  {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_MFP2INT, F_FPTYPE | F_SF},
+  {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_MINT2FP, F_FPTYPE | F_SF},
   {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
   {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
   {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},