[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
Marcus Shawcroft
marcus.shawcroft@gmail.com
Mon Dec 14 16:04:00 GMT 2015
On 11 December 2015 at 12:05, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:
> gas/testsuite/
> 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
>
> * gas/aarch64/advsimd-fp16.d: Update expected output.
> * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register
> misc.
> instructions.
>
> opcodes/
> 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
>
> * aarch64-asm-2.c: Regenerate.
> * aarch64-dis-2.c: Regenerate.
> * aarch64-opc-2.c: Regenerate.
> * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
> (QL_S_2SAMEH): New.
> (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
> fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
> frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
> fcvtzu and frsqrte to the scalar two register misc. group.
>
OK /Marcus
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