[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.

[Marcus Shawcroft]

On 11 December 2015 at 12:03, Matthew Wahab <matthew.wahab@foss.arm.com> wrote:

> gas/testsuite/
> 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * gas/aarch64/advsimd-fp16.d: Update expected output.
>         * gas/aarch64/advsimd-fp16.s: Add tests for vector two register
> misc.
>         instructions.
>
> opcodes/
> 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
>
>         * aarch64-asm-2.c: Regenerate.
>         * aarch64-dis-2.c: Regenerate.
>         * aarch64-opc-2.c: Regenerate.
>         * aarch64-tbl.h (QL_V2SAMEH): New.
>         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
>         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
>         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
>         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
>         and fsqrt to the vector register misc. group.
>

OK /Marcus