[PATCH, AArch64] Generic support for all system registers using mrs and msr

[Jiong Wang]

this patch relax the restrictions on operand format of msr/mrs to accept
all opearnds in the following canonical format:

   S<op0>_<op1>_<Cn>_<Cm>_<op2>

before this patch:
   * msr/mrs only support op0 be 3.
   * for op0 be 0/1/2, there are supported by pseudo instructions,
     SYS/SYSL/HINT/CLREX etc.

after this patch:
   * all old pseudo instructions are not affected.
   * you can also use msr/mrs with operands of canonical format.

for decoding, if the op0/op1/Cn/Cm/op2 combination falls into related
pseudo instructions, then the pseudo instructions disassembly is prefered.

for example

   msr     s1_7_C15_C15_7, x27

will be disassembled into:

   sys     #7, C15, C15, #7, x27

ok to install?

opcode/
   * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
   * aarch64-dis-2.c: Update auto-generated file.

gas/
   * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0 field.

gas/testsuite/
   * gas/aarch64/illegal.s: Update testcase.
   * gas/aarch64/illegal.d: Likewise.
   * gas/aarch64/sysreg-1.s: Likewise.
   * gas/aarch64/sysreg-1.d: Likewise.
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