[Patch][AArch64] - Error on load pair to same register

Ryan Mansfield rmansfield@qnx.com
Wed Nov 12 20:07:00 GMT 2014


I came across a SIGILL at runtime caused by a typo specifying the same 
register in a load pair.

The ARM DDI 0487A says on page C6-507

if memop == MemOp_LOAD && t == t2 then
	Constraint c = ConstrainUnpredictable();
	assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
	case c of
		when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN
		when Constraint_UNDEF UnallocatedEncoding();
		when Constraint_NOP EndOfInstruction();

I doubt that any one would intentionally do this operation since the 
behaviour is unpredictable so it just seems safer to reject the code.

2014-11-12  Ryan Mansfield  <rmansfield@qnx.com>

         * aarch64-opc.c (operand_general_constraint_met_p): Add constraint
         that load pair must have different registers.


Ryan Mansfield
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