[PATCH] Fixing issue with "Rearrange MIPS INSN* masks" patch

[Richard Sandiford]

Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> 2014-05-05  Andrew Bennett  <andrew.bennett@imgtec.com>
>
>                 * mips-opc.c (G3): Remove I4.
>
>
> diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
> index 9181c3f..f3b287f 100644
> --- a/opcodes/mips-opc.c
> +++ b/opcodes/mips-opc.c
> @@ -296,8 +296,7 @@ decode_mips_operand (const char *p)
> #define G2      (T3             \
>                   )
>
> -#define G3      (I4             \
> -                 |EE            \
> +#define G3      (EE             \
>                   )
>
>  /* 64 bit CPU with 32 bit FPU (single float). */

Might as well make it:

#define G3      EE

OK with that change, thanks.

Richard