[PATCH] Add support for MIPS eretnc MIPS32r5 instruction

[Matthew Fortune]

>  /* We cannot start at zero due to ISA_UNKNOWN below.  */
>  #define INSN_ISA1                 1
> @@ -1079,6 +1079,10 @@ struct mips_opcode
>  #define INSN_ISA4_32              12
>  #define INSN_ISA4_32R2            13
>  #define INSN_ISA5_32R2            14
> +#define INSN_ISA32R3              15
> +#define INSN_ISA32R5              16
> +#define INSN_ISA64R3              17
> +#define INSN_ISA64R5              18

These are in the wrong position. They should appear in the first section of
the list, re-number the rest and update the table accordingly. The
mips_isa_table contains an entry for each real ISA with the value representing
which of the full set of ISAs + ISA combinations include that ISA. The comment
also needs updating when that is done.

> 
>  /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
>     INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
> @@ -1089,7 +1093,8 @@ struct mips_opcode
>     (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
>     is non-zero.  */
>  static const unsigned int mips_isa_table[] =
> -  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
> +  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff,
> +    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7e63, 0xfe63, 0x17fff, 0x3ffff };

Update as above.