[PATCH] ARM/opcodes: Fix negative hexadecimal offset disassembly

[Maciej W. Rozycki]

Hi,

 This piece of code was somehow lost in our internal merges and did not 
make it to commit 26d97720ed597caf769e6f16e6e7c1f8e385f9c7.  It corrects 
the hexadecimal offset disassembled in a comment for GPR-relative memory 
access instructions to match the actual offset and what is printed for 
other instructions, as indicated by the test suite changes included.

 Regression-tested with arm-aout, arm-coff, arm-epoc-pe, arm-linuxeabi, 
arm-netbsdelf, arm-nto, arm-pe, arm-symbianelf, arm-vxworks and 
arm-wince-pe.  OK to apply?

2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	opcodes/
	* arm-dis.c (print_arm_address): Negate the GPR-relative offset
	returned if the U bit is set.

2014-08-21  Paul Brook  <paul@codesourcery.com>

	gas/testsuite/
	* gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
	offset fix.
	* gas/arm/arch7r-mp.d: Likewise.

  Maciej

binutils-opcodes-arm-negative-offset-fixup.diff
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/arm/arch7a-mp.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/arm/arch7a-mp.d	2013-04-23 18:26:09.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/arm/arch7a-mp.d	2014-04-04 01:41:16.237837735 +0100
@@ -11,7 +11,7 @@
 0[0-9a-f]+ <[^>]+> f59ef000 	pldw	\[lr\]
 0[0-9a-f]+ <[^>]+> f591f000 	pldw	\[r1\]
 0[0-9a-f]+ <[^>]+> f590ffff 	pldw	\[r0, #4095\]	; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff 	pldw	\[r0, #-4095\]	; 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff 	pldw	\[r0, #-4095\]	; 0xfffff001
 0[0-9a-f]+ <[^>]+> f790f000 	pldw	\[r0, r0\]
 0[0-9a-f]+ <[^>]+> f791f000 	pldw	\[r1, r0\]
 0[0-9a-f]+ <[^>]+> f79ef000 	pldw	\[lr, r0\]
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/arm/arch7r-mp.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/arm/arch7r-mp.d	2011-10-04 15:29:06.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/arm/arch7r-mp.d	2014-04-04 01:41:16.237837735 +0100
@@ -10,7 +10,7 @@
 0[0-9a-f]+ <[^>]+> f59ef000 	pldw	\[lr\]
 0[0-9a-f]+ <[^>]+> f591f000 	pldw	\[r1\]
 0[0-9a-f]+ <[^>]+> f590ffff 	pldw	\[r0, #4095\]	; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff 	pldw	\[r0, #-4095\]	; 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff 	pldw	\[r0, #-4095\]	; 0xfffff001
 0[0-9a-f]+ <[^>]+> f790f000 	pldw	\[r0, r0\]
 0[0-9a-f]+ <[^>]+> f791f000 	pldw	\[r1, r0\]
 0[0-9a-f]+ <[^>]+> f79ef000 	pldw	\[lr, r0\]
Index: binutils-fsf-trunk-quilt/opcodes/arm-dis.c
===================================================================
--- binutils-fsf-trunk-quilt.orig/opcodes/arm-dis.c	2014-03-24 22:25:10.769016188 +0000
+++ binutils-fsf-trunk-quilt/opcodes/arm-dis.c	2014-04-04 01:41:16.237837735 +0100
@@ -2583,6 +2583,8 @@ print_arm_address (bfd_vma pc, struct di
 	      arm_decode_shift (given, func, stream, TRUE);
 	    }
 	}
+      if (NEGATIVE_BIT_SET)
+	offset = -offset;
     }
 
   return (signed long) offset;