[COMMITTED][AArch64] Fix off by one error in instruction relaxation mask.

[Marcus Shawcroft]

Hi,

The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to
ensure that destination register in a relaxed ldr instruction is
always X0.  The mask has an off by one error resulting in the most
significant bit of the destination register being retained in the
relaxed instruction.  The issue generally appears when the compiler
emits TLS accesses code under high register pressure resulting in a
broken code sequence.

Tested on aarch64-none-linux-gnu.  Committed.

I'll back port to 2.24 shortly.

/Marcus

ld 
 

 
 

2014-04-15  Marcus Shawcroft  <marcus.shawcroft@arm.com>

         * (elfNN_aarch64_tls_relax): Fix instruction mask.
 
 

ld/testsuite 
 


2014-04-15  Marcus Shawcroft  <marcus.shawcroft@arm.com>

         * ld-aarch64/tls-relax-gdesc-ie.s (var): Adjust test case
         to include all 5 bits of LDR destination register.
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