[PATCH] AARCH64 add GICv3 system registers

[Andrew Pinski]

Hi,
  This patch adds the GICv3 system registers names to the list of
system register names.  Naveen wrote the patch but I am submitting it.

OK?  Tested for aarch64-linux-gnu with no regressions.

Thanks,
Andrew Pinski

ChangeLog:

AArch64: Add support for GIC ICC_* system registers in gas

2013-09-25  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

* aarch64-opc.c (aarch64_sys_regs): Add support for GIC ICC_*
system registers in gas.

PS I will update the date in the changelog before committing it once approved.
-------------- next part --------------
? .aarch64-opc.c.swp
? b
? opcodes
Index: aarch64-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/aarch64-opc.c,v
retrieving revision 1.9
diff -u -p -r1.9 aarch64-opc.c
--- aarch64-opc.c	28 Aug 2013 10:25:36 -0000	1.9
+++ aarch64-opc.c	25 Sep 2013 18:47:03 -0000
@@ -2985,6 +2985,70 @@ const struct aarch64_name_value_pair aar
   { "pmevtyper29_el0",   CPENC(3,3,C14,C15,5) },
   { "pmevtyper30_el0",   CPENC(3,3,C14,C15,6) },
   { "pmccfiltr_el0",     CPENC(3,3,C14,C15,7) },
+
+  /* GICv3 system registers */
+  { "icc_iar1_el1",	 CPENC(3,0,C12,C12,0) },
+  { "icc_iar0_el1",	 CPENC(3,0,C12,C8,0) },
+  { "icc_eoir1_el1",	 CPENC(3,0,C12,C12,1) },
+  { "icc_eoir0_el1",	 CPENC(3,0,C12,C8,1) },
+  { "icc_hppir1_el1",	 CPENC(3,0,C12,C12,2) },
+  { "icc_hppir0_el1",	 CPENC(3,0,C12,C8,2) },
+  { "icc_bpr1_el1",	 CPENC(3,0,C12,C12,3) },
+  { "icc_bpr0_el1",	 CPENC(3,0,C12,C8,3) },
+  { "icc_dir_el1",	 CPENC(3,0,C12,C11,1) },
+  { "icc_pmr_el1",	 CPENC(3,0,C4,C6,0) },
+  { "icc_rpr_el1",	 CPENC(3,0,C12,C11,3) },
+  { "icc_ctlr_el1",	 CPENC(3,0,C12,C12,4) },
+  { "icc_ctlr_el3",	 CPENC(3,6,C12,C12,4) },
+  { "icc_sre_el1",	 CPENC(3,0,C12,C12,5) },
+  { "icc_sre_el2",	 CPENC(3,4,C12,C9,5) },
+  { "icc_sre_el3",	 CPENC(3,6,C12,C12,5) },
+  { "icc_igrpen0_el1",	 CPENC(3,0,C12,C12,6) },
+  { "icc_igrpen1_el1",	 CPENC(3,0,C12,C12,7) },
+  { "icc_igrpen1_el3",	 CPENC(3,6,C12,C12,7) },
+  { "icc_seien_el1",	 CPENC(3,0,C12,C13,0) },
+  { "icc_sgi1r_el1",	 CPENC(3,0,C12,C11,5) },
+  { "icc_asgi1r_el1",	 CPENC(3,0,C12,C11,6) },
+  { "icc_sgi0r_el1",	 CPENC(3,0,C12,C11,7) },
+  { "icc_ap0r0_el1",	 CPENC(3,0,C12,C8,4) },
+  { "icc_ap0r1_el1",	 CPENC(3,0,C12,C8,5) },
+  { "icc_ap0r2_el1",	 CPENC(3,0,C12,C8,6) },
+  { "icc_ap0r3_el1",	 CPENC(3,0,C12,C8,7) },
+  { "icc_ap1r0_el1",	 CPENC(3,0,C12,C9,0) },
+  { "icc_ap1r1_el1",	 CPENC(3,0,C12,C9,1) },
+  { "icc_ap1r2_el1",	 CPENC(3,0,C12,C9,2) },
+  { "icc_ap1r3_el1",	 CPENC(3,0,C12,C9,3) },
+  { "ich_ap0r0_el2",	 CPENC(3,4,C12,C8,0) },
+  { "ich_ap0r1_el2",	 CPENC(3,4,C12,C8,1) },
+  { "ich_ap0r2_el2",	 CPENC(3,4,C12,C8,2) },
+  { "ich_ap0r3_el2",	 CPENC(3,4,C12,C8,3) },
+  { "ich_ap1r0_el2",	 CPENC(3,4,C12,C9,0) },
+  { "ich_ap1r1_el2",	 CPENC(3,4,C12,C9,1) },
+  { "ich_ap1r2_el2",	 CPENC(3,4,C12,C9,2) },
+  { "ich_ap1r3_el2",	 CPENC(3,4,C12,C9,3) },
+  { "ich_hcr_el2",	 CPENC(3,4,C12,C11,0) },
+  { "ich_vtr_el2",	 CPENC(3,4,C12,C11,1) },
+  { "ich_misr_el2",	 CPENC(3,4,C12,C11,2) },
+  { "ich_eisr_el2",	 CPENC(3,4,C12,C11,3) },
+  { "ich_elsr_el2",	 CPENC(3,4,C12,C11,5) },
+  { "ich_vmcr_el2",	 CPENC(3,4,C12,C11,7) },
+  { "ich_vseir_el2",	 CPENC(3,4,C12,C9,4) },
+  { "ich_lr0_el2",	 CPENC(3,4,C12,C12,0) },
+  { "ich_lr1_el2",	 CPENC(3,4,C12,C12,1) },
+  { "ich_lr2_el2",	 CPENC(3,4,C12,C12,2) },
+  { "ich_lr3_el2",	 CPENC(3,4,C12,C12,3) },
+  { "ich_lr4_el2",	 CPENC(3,4,C12,C12,4) },
+  { "ich_lr5_el2",	 CPENC(3,4,C12,C12,5) },
+  { "ich_lr6_el2",	 CPENC(3,4,C12,C12,6) },
+  { "ich_lr7_el2",	 CPENC(3,4,C12,C12,7) },
+  { "ich_lr8_el2",	 CPENC(3,4,C12,C13,0) },
+  { "ich_lr9_el2",	 CPENC(3,4,C12,C13,1) },
+  { "ich_lr10_el2",	 CPENC(3,4,C12,C13,2) },
+  { "ich_lr11_el2",	 CPENC(3,4,C12,C13,3) },
+  { "ich_lr12_el2",	 CPENC(3,4,C12,C13,4) },
+  { "ich_lr13_el2",	 CPENC(3,4,C12,C13,5) },
+  { "ich_lr14_el2",	 CPENC(3,4,C12,C13,6) },
+  { "ich_lr15_el2",	 CPENC(3,4,C12,C13,7) },
   { 0,          CPENC(0,0,0,0,0)  },
 };