[PATCH 5/6] x86/MPX: fix operand size handling

[H.J. Lu]

On Thu, Oct 10, 2013 at 8:14 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Oct 10, 2013 at 6:14 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 09.10.13 at 17:51, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>>>>> need to encode this bit nor should disassemble with 32-bit register
>>>>>> operands.
>>>>>>
>>>>>> No MPX instructions would ever take a 16-bit register operand.
>>>>>>
>>>>>> gas/
>>>>>> 2013-10-08  Jan Beulich <jbeulich@suse.com>
>>>>>>
>>>>>>         * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>>>>>         to MPX instructions in 64-bit mode.
>>>>>
>>>>> I think it should be an error.
>>>>
>>>> I can certainly change that - a warning just seemed a better match
>>>> to hardware ignoring operand size here.
>>>
>>> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
>>> similar to mov with debug registers.  Let's do that instead.
>>
>> Here's  the updated patch.
>>
>> Jan
>>
>> General purpose register operands of MPX instructions can only ever be
>> native size ones.
>>
>> opcodes/
>> 2013-10-08  Jan Beulich <jbeulich@suse.com>
>>
>>         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
>>         default case.
>>         (OP_E_register): Move v_bnd_mode alongside m_mode.
>>         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
>>         Drop Reg16 and Disp16. Add NoRex64.
>>         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
>>         * i386-tbl.h: Re-generate.
>>
>
> It is OK.
>

I checked it in with testcase updates.

Thanks.



-- 
H.J.