[MIPS] Add new virtualization instructions

Andrew Pinski andrew.pinski@caviumnetworks.com
Thu May 9 18:02:00 GMT 2013


On Thu, May 9, 2013 at 10:39 AM, David Daney <ddaney@caviumnetworks.com> wrote:
> On 05/08/2013 04:50 PM, Pinski, Andrew wrote:
> [...]
>
>> gas/ChangeLog:
>> * config/tc-mips.c (struct mips_set_options): New ase_virt field.
>> (mips_opts): Update for the new field.
>> (file_ase_virt): New variable.
>> (ISA_SUPPORTS_VIRT_ASE): New macro.
>> (MIPS_CPU_ASE_VIRT): New define.
>> (is_opcode_valid): Handle ase_virt.
>> (macro_build): Handle "+J".
>> (validate_mips_insn): Likewise.
>> (mips_ip): Likewise.
>> (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
>> (md_longopts): Add mvirt and mnovirt
>> (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
>> (mips_after_parse_args): Handle ase_virt field.
>> (s_mipsset): Handle "virt" and "novirt".
>> (mips_elf_final_processing): Add a comment about virt ASE might need a new
>> flag.
>> (md_show_usage): Print out the usage of -mvirt and mno-virt options.
>>
>> gas/testsuite/ChangeLog:
>> * gas/mips/mips.exp: Run virt testcase also.
>> * gas/mips/virt.d: New file.
>> * gas/mips/virt.s: New file.
>>
>> include/opcode/ChangeLog:
>> * mips.h (OP_MASK_CODE10): Correct definition.
>> (OP_SH_CODE10): Likewise.
>> Add a comment that "+J" is used now for OP_*CODE10.
>> (INSN_ASE_MASK): Update.
>> (INSN_VIRT): New macro.
>>
>> opcodes/ChangeLog:
>> * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 and mips64r2.
>> (print_insn_args): Handle "+J".
>> * mips-opc.c (IVIRT): New define.
>> (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
>> tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
>> Move rfe to the bottom as it conflicts with tlbgp.
>
> [...]
>>
>> ===================================================================
>> RCS file: /cvs/src/src/gas/config/tc-mips.c,v
>> retrieving revision 1.531
>> diff -u -p -r1.531 tc-mips.c
>> --- gas/config/tc-mips.c        6 May 2013 15:25:45 -0000       1.531
>> +++ gas/config/tc-mips.c        8 May 2013 23:16:15 -0000
>
> [...]
>>
>> @@ -1395,6 +1404,8 @@ struct mips_cpu_info
>>   #define MIPS_CPU_ASE_MDMX     0x0020  /* CPU implements MDMX ASE */
>>   #define MIPS_CPU_ASE_DSPR2    0x0040  /* CPU implements DSP R2 ASE */
>>   #define MIPS_CPU_ASE_MCU      0x0080  /* CPU implements MCU ASE */
>> +#define MIPS_CPU_ASE_VIRT      0x0100  /* CPU implements Virtualization
>> ASE */
>> +#define MIPS_CPU_FLOAT_OPS_NONE        0x0200  /* CPU has no FPU */
>
>
> This MIPS_CPU_FLOAT_OPS_NONE appears to be unrelated to the rest of the
> patch.  Did it accidentally leak in here?

I removed it but I forgot to recreate the patch.

-- Pinski


>
> David Daney
>
>



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