Fix some MIPS operand typos
Maciej W. Rozycki
macro@codesourcery.com
Tue Jun 25 22:56:00 GMT 2013
On Sun, 23 Jun 2013, Richard Sandiford wrote:
> Index: include/opcode/mips.h
> ===================================================================
> --- include/opcode/mips.h 2013-06-23 16:12:03.048236213 +0100
> +++ include/opcode/mips.h 2013-06-23 20:49:32.410068693 +0100
> @@ -1811,7 +1811,7 @@ #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
>
> Coprocessor instructions:
> "E" 5-bit target register (MICROMIPSOP_*_RT)
> - "G" 5-bit destination register (MICROMIPSOP_*_RD)
> + "G" 5-bit destination register (MICROMIPSOP_*_RS)
> "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
> "+D" combined destination register ("G") and sel ("H") for CP0 ops,
> for pretty-printing in disassembly only
Good catch, s/destination/source/ for consistency with the field name
might seem desirable too. However I think merely expanding field names
here is counterproductive. How about giving meaningful descriptions here?
2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
include/opcode/
* mips.h: Refer to general and coprocessor registers in
coprocessor instruction field documentation.
Maciej
binutils-mips-include-ops-doc.diff
Index: binutils-fsf-trunk-quilt/include/opcode/mips.h
===================================================================
--- binutils-fsf-trunk-quilt.orig/include/opcode/mips.h 2013-06-25 01:09:04.000000000 +0100
+++ binutils-fsf-trunk-quilt/include/opcode/mips.h 2013-06-25 23:50:55.211225703 +0100
@@ -441,14 +441,14 @@ struct mips_opcode
"W" 5 bit same register used as floating target and destination (OP_*_FT)
Coprocessor instructions:
- "E" 5 bit target register (OP_*_RT)
- "G" 5 bit destination register (OP_*_RD)
+ "E" 5 bit general register (OP_*_RT)
+ "G" 5 bit coprocessor register (OP_*_RD)
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
see also "k" above
- "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
+ "+D" Combined coprocessor register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only.
Macro instructions:
@@ -1813,10 +1813,10 @@ extern const int bfd_mips16_num_opcodes;
(MICROMIPSOP_*_FS)
Coprocessor instructions:
- "E" 5-bit target register (MICROMIPSOP_*_RT)
- "G" 5-bit destination register (MICROMIPSOP_*_RS)
+ "E" 5-bit general register (MICROMIPSOP_*_RT)
+ "G" 5-bit coprocessor register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
- "+D" combined destination register ("G") and sel ("H") for CP0 ops,
+ "+D" combined coprocessor register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only
Macro instructions:
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