[RL78] Fix encoding of divwu insn

nick clifton nickc@redhat.com
Fri Feb 22 15:18:00 GMT 2013


Hi Kaushik,

> Please find below a small patch that fixes the opcode generated for the "divwu"
> instruction for the RL78 target. This would be as per the opcode table provided
> by Renesas (Table 5.6 of RL78 Software Manual Rev.1.00 Jan 2011)

We appears to have different versions of this document.

I have document number: R01US0015EJ0100 Rev.1.00 from Jan 31, 2011. 
Table 5.6 of this document shows DIVWU as being encoded as 0xCE, 0xFB, 
0x04.  (This is on page 67 of the document).

>   	| DIVWU
> -	  { B3 (0xce, 0xfb, 0x04); }
> +	  { B3 (0xce, 0xfb, 0x0b); }

I also have an old document from 2010 that shows DIVWU mapped to 
0xce,0xfb,0x0b but that also shows a DIVH instruction being mapped to 
0xce,0xfb,0x04.  The R01US0015EJ0100 document has no mention of a DIVH 
instruction.

Please can you confirm the document number of the Software Manual that 
you are using, and tell me if it shows any instruction being mapped to 
0xce.0xfb,0x04.

Cheers
     Nick







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