PATCH: PR gas/15159: Implement Intel SMAP instruction support
H.J. Lu
hongjiu.lu@intel.com
Tue Feb 19 19:13:00 GMT 2013
Hi,
I checked in this patch to implement Intel SMAP instruction support.
H.J.
---
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1a3ec06..49c3b35 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/15159
+ * config/tc-i386.c (cpu_arch): Add ".smap".
+
+ * doc/c-i386.texi: Document smap.
+
2013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (s_cpload): Call mips_mark_labels and set
@@ -11,7 +18,7 @@
2013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * config/tc-arm.c (do_neon_mov): Break on NS_NULL.
+ * config/tc-arm.c (do_neon_mov): Break on NS_NULL.
2013-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
@@ -33,7 +40,7 @@
core.
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
- Andrew Jenner <andrew@codesourcery.com>
+ Andrew Jenner <andrew@codesourcery.com>
Based on patches from Altera Corporation.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c8ec0c0..737cc2e 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -782,6 +782,8 @@ static const arch_entry cpu_arch[] =
CPU_RDSEED_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
CPU_PRFCHW_FLAGS, 0, 0 },
+ { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
+ CPU_SMAP_FLAGS, 0, 0 },
};
#ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index f68cca2..9aae847 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -149,6 +149,7 @@ accept various extension mnemonics. For example,
@code{adx},
@code{rdseed},
@code{prfchw},
+@code{smap},
@code{noavx},
@code{vmx},
@code{vmfunc},
@@ -1027,6 +1028,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
+@item @samp{.smap}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 8027428..4508042 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/15159
+ * gas/i386/i386.exp: Run smap and x86-64-smap.
+
+ * gas/i386/smap.d: New file.
+ * gas/i386/smap.s: likewise.
+ * gas/i386/x86-64-smap.d: likewise.
+
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
* gas/metag/labelarithmetic.d: Fix the expected disassembler
@@ -13,9 +22,9 @@
2013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * gas/arm/neon-vmov-bad.d: New file.
- * gas/arm/neon-vmov-bad.s: Likewise.
- * gas/arm/neon-vmov-bad.l: Likewise.
+ * gas/arm/neon-vmov-bad.d: New file.
+ * gas/arm/neon-vmov-bad.s: Likewise.
+ * gas/arm/neon-vmov-bad.l: Likewise.
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
@@ -47,7 +56,7 @@
(run_list_test): Delete. Adjust callers to use standard version.
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
- Andrew Jenner <andrew@codesourcery.com>
+ Andrew Jenner <andrew@codesourcery.com>
Based on patches from Altera Corporation.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 6daf559..f03dcf3 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -243,6 +243,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "rdseed-intel"
run_dump_test "prefetch"
run_dump_test "prefetch-intel"
+ run_dump_test "smap"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@@ -502,6 +503,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-rdseed-intel"
run_dump_test "x86-64-prefetch"
run_dump_test "x86-64-prefetch-intel"
+ run_dump_test "x86-64-smap"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/smap.d b/gas/testsuite/gas/i386/smap.d
new file mode 100644
index 0000000..16ae63a
--- /dev/null
+++ b/gas/testsuite/gas/i386/smap.d
@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 SMAP
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 0f 01 ca clac
+[ ]*[a-f0-9]+: 0f 01 cb stac
+#pass
diff --git a/gas/testsuite/gas/i386/smap.s b/gas/testsuite/gas/i386/smap.s
new file mode 100644
index 0000000..1864cee
--- /dev/null
+++ b/gas/testsuite/gas/i386/smap.s
@@ -0,0 +1,6 @@
+# SMAP Instructions
+
+ .text
+foo:
+ clac
+ stac
diff --git a/gas/testsuite/gas/i386/x86-64-smap.d b/gas/testsuite/gas/i386/x86-64-smap.d
new file mode 100644
index 0000000..639bc31
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-smap.d
@@ -0,0 +1,12 @@
+#source: smap.s
+#objdump: -dw
+#name: 64bit SMAP
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 0f 01 ca clac
+[ ]*[a-f0-9]+: 0f 01 cb stac
+#pass
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1400b96..3e75abf 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,19 @@
+2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/15159
+ * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
+
+ * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
+ (cpu_flags): Add CpuSMAP.
+
+ * i386-opc.h (CpuSMAP): New.
+ (i386_cpu_flags): Add cpusmap.
+
+ * i386-opc.tbl: Add clac and stac.
+
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
* metag-dis.c: Initialize outf->bytes_per_chunk to 4
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f8e62aa..5a77255 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -10600,6 +10600,8 @@ static const struct dis386 rm_table[][8] = {
/* RM_0F01_REG_1 */
{ "monitor", { { OP_Monitor, 0 } } },
{ "mwait", { { OP_Mwait, 0 } } },
+ { "clac", { Skip_MODRM } },
+ { "stac", { Skip_MODRM } },
},
{
/* RM_0F01_REG_2 */
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 7f66a1e..3e7481b 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -206,6 +206,8 @@ static initializer cpu_flag_init[] =
"CpuRdSeed" },
{ "CPU_PRFCHW_FLAGS",
"CpuPRFCHW" },
+ { "CPU_SMAP_FLAGS",
+ "CpuSMAP" },
};
static initializer operand_type_init[] =
@@ -379,6 +381,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuRDSEED),
BITFIELD (CpuADX),
BITFIELD (CpuPRFCHW),
+ BITFIELD (CpuSMAP),
BITFIELD (Cpu64),
BITFIELD (CpuNo64),
#ifdef CpuUnused
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index bfb3ce4..ff99eeb 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -152,6 +152,8 @@ enum
CpuADX,
/* Supports prefetchw and prefetch instructions. */
CpuPRFCHW,
+ /* SMAP instructions required. */
+ CpuSMAP,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
@@ -235,6 +237,7 @@ typedef union i386_cpu_flags
unsigned int cpurdseed:1;
unsigned int cpuadx:1;
unsigned int cpuprfchw:1;
+ unsigned int cpusmap:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3e871fb..11e2615 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3053,3 +3053,7 @@ xstore, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N
adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
rdseed, 1, 0xfc7, 0x7, 2, CpuRdSeed, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
+
+// SMAP instructions.
+clac, 0, 0xf01, 0xca, 2, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
+stac, 0, 0xf01, 0xcb, 2, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
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