[PATCH] arm: allow SIMD instructions to be used without VFP support enabled

[Richard Earnshaw]

On 09/04/13 08:03, Jan Beulich wrote:
>>>> On 08.04.13 at 18:31, Richard Earnshaw <rearnsha@arm.com> wrote:
>> The class of common mnemonics you've changed includes instructions such
>> as vmul.  When you have Neon but no FP, both the scalar FP and vector FP
>> variants of the instructions should be disabled, but the integer
>> versions remain.
>
> By example of vabs I already know that this isn't the case -
> vabs.f32 (with Dn or Qn register operands) continues to assemble
> quite fine.
>
> The fundamental question here is what the meaning of
>
> 	.arch_extension "fp"
>
> and its "nofp" counterpart really is: The current meaning is to
> enable/disable VFP, not floating point support in general. And
> again, according to my reading of the spec you'd need a
> separate enable/disable for SIMD-without-FP first in order to
> achieve the effect you appear to aim at (iow to me "no VFP"
> does not imply integer only SIMD, no matter whether in actual
> implementations this will likely be the case, as there's no
> dependency mentioned in the FPSID and MVFRx registers).
>

The only thing that's useful to think about is what is permitted by the 
architecture.  The architecture only permits INT_NEON + FP_NEON + FP, FP 
(in various guises) and INT_NEON.  It doesn't make sense to me to allow 
other random permutations.  Ergo

	.arch_extension "neon"
	.arch_extension "nofp"

should give INT_NEON in the terminology above.

R.