[PATCH, RFC] arm: VMRS and VMSR should accept FPINST{,2}

[Jan Beulich]

The Common VFP Subarchitecture specification has two more FP control registers
which are to be accessed through VMRS and VMSR. The assembler, however, so far
didn't provide a way to encode the respective instructions (other than through
legacy mnemonics or the hard to read MRC/MCR ones).

With Common VFP and VFP apparently not being the same thing, and there not
being any way currently to specify the Common VFP Subarchitecture version, I
tied acceptance of these registers to VFPv3 being enabled. The patch is RFC
because of my need of confirmation whether that's acceptable, or whether
there's a mechanism is failed to spot.

gas/
2013-04-08  Jan Beulich <jbeulich@suse.com>

	* gas/config/tc-arm.c (do_vmrs): Also accept FPINST and FPINST2.
	(do_vmsr): Likewise.

--- 2013-04-08/gas/config/tc-arm.c
+++ 2013-04-08/gas/config/tc-arm.c
@@ -8271,6 +8271,11 @@ do_vmrs (void)
 
   switch (inst.operands[1].reg)
     {
+    case  9: /* FPINST */
+    case 10: /* FPINST2 */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd/*???*/),
+		  _("operand 1 invalid for the selected VFP architecure"));
+      /* fall through */
     case 0: /* FPSID */
     case 1: /* FPSCR */
     case 6: /* MVFR1 */
@@ -8300,13 +8305,18 @@ do_vmsr (void)
 
   switch (inst.operands[0].reg)
     {
+    case  9: /* FPINST */
+    case 10: /* FPINST2 */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd/*???*/),
+		  _("operand 0 invalid for the selected VFP architecure"));
+      /* fall through */
     case 0: /* FPSID  */
     case 1: /* FPSCR  */
     case 8: /* FPEXC */
       inst.instruction |= (inst.operands[0].reg << 16);
       break;
     default:
-      first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
+      first_error (_("operand 0 must be a writable VFP extension System Register"));
     }
 
   inst.instruction |= (Rt << 12);



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