[PATCH] arm: permit certain VMOV kinds without suffix

[Jan Beulich]

The specification explicitly permits VMOV without size/data type suffix for
the case of moving between scalar and core register. The easiest way to deal
with that appeared to be to fake the suffix if none was specified.

gas/
2013-04-08  Jan Beulich <jbeulich@suse.com>

	* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
	if there was none specified for moves between scalar and core
	register.

--- 2013-04-08/gas/config/tc-arm.c
+++ 2013-04-08/gas/config/tc-arm.c
@@ -15360,6 +15360,16 @@ do_neon_mov (void)
         unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
         unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
 
+	/* .<size> is optional here, defaulting to .32. */
+	if (inst.vectype.elems == 0
+	    && inst.operands[0].vectype.type == NT_invtype
+	    && inst.operands[1].vectype.type == NT_invtype)
+	  {
+	    inst.vectype.el[0].type = NT_untyped;
+	    inst.vectype.el[0].size = 32;
+	    inst.vectype.elems = 1;
+	  }
+
         et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
         logsize = neon_logbits (et.size);
 
@@ -15409,6 +15419,16 @@ do_neon_mov (void)
         unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
         unsigned abcdebits = 0;
 
+	/* .<dt> is optional here, defaulting to .32. */
+	if (inst.vectype.elems == 0
+	    && inst.operands[0].vectype.type == NT_invtype
+	    && inst.operands[1].vectype.type == NT_invtype)
+	  {
+	    inst.vectype.el[0].type = NT_untyped;
+	    inst.vectype.el[0].size = 32;
+	    inst.vectype.elems = 1;
+	  }
+
 	et = neon_check_type (2, NS_NULL,
 			      N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
         logsize = neon_logbits (et.size);



-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: binutils-mainline-arm-vmov.patch
URL: <https://sourceware.org/pipermail/binutils/attachments/20130408/f1571ac5/attachment.ksh>