[RFA] PowerPC E5500 and E6500 support

[Edmar]

Freescale would like to contribute this patch to binutils.

It enables binutils for E5500 and E6500 cores.
Both are 64 bit cores capable to execute popcntb/w/d, bperm,
cmpb, and prtyw/d instructions.
The e6500 core has Altivec and the new Altivec instructions that
will be part of Power ISA-2.07.
A test case for the new E6500 core specific instructions as well as the
new Altivec instructions is provided.

This patch also customize "nop" terminations for the whole e500mc series.
Test cases are provided.

The patch was tested for powerpc 32 bits and 64 bits with no regressions
against binutils-2.22.52 snapshot from Feb 21st.

We thanks in advance for your time to review and commit the patch.

Regards,
Edmar

ChangeLog
2012-02-23  Edmar Wienskoski <edmar@freescale.com>

     * include/opcode/ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500,
     PPC_OPCODE_TMR.

bfd/ChangeLog
2012-02-23  Edmar Wienskoski <edmar@freescale.com>

     * archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
     * bfd-in2.h: Regenerate.
     * cpu-powerpc.c (bfd_powerpc_archs): Add entryies for
     bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.

gas/ChangeLog
2012-02-23  Edmar Wienskoski <edmar@freescale.com>

     * config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500.
     (ppc_handle_align): Add termination nop opcode for e500mc family.
     * gas/doc/as.texinfo: Document options -me5500 and -me6500.
     * gas/doc/c-ppc.texi: Document options -me5500 and -me6500.

opcodes/ChangeLog
2012-02-23  Edmar Wienskoski <edmar@freescale.com>

     * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
     * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
     (PPCVEC2, PPCTMR, E6500): New short names.
     (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
     mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
     lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
     lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
     lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
     optional operands on sync instruction for E6500 target.

gas/testsuite/ChangeLog
2012-02-23  Edmar Wienskoski <edmar@freescale.com>

     * gas/ppc/e500mc64_nop.s: New test case for e500mc family
     termination nops.
     * gas/ppc/e500mc64_nop.d: Likewise.
     * gas/ppc/e5500_nop.s: Likewise.
     * gas/ppc/e5500_nop.d: Likewise.
     * gas/ppc/e6500_nop.s: Likewise.
     * gas/ppc/e6500_nop.d: Likewise.
     * gas/ppc/e6500.s: New.
     * gas/ppc/e6500.d: Likewise.
     * gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and
     e6500_nop.

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