[RFA] PowerPC VLE port - opcodes update
Maciej W. Rozycki
macro@codesourcery.com
Fri Aug 31 11:03:00 GMT 2012
Peter,
> Unfortunately, this isn't the only occurrence of two instructions with the same
> major and minor opcodes that are enabled at the same time with -mvle. There are
> actually quite a few of them. :( Doing a quick scan, I see these conflicting
> instructions:
>
> {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
> {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
[etc...]
All these instructions are valid in the VLE mode depending on what a
given processor implements. The logic to interpret the PPCVLE
(PPC_OPCODE_VLE) flag should IMHO be changed such that in the VLE mode
(-mvle) it does not enable any instruction such marked unconditionally.
The flag should mean an instruction is merely permitted in the VLE mode
and then other flags would actually drive enabling the instruction -- an
extra opcode flag might be required to enable base set VLE instructions
that are always available with a lone -mvle option as I reckon they are a
superset of the base standard Power instruction set. That flag, say
PPC_OPCODE_VLE_BASE or PPCVLEB, would be ORed in the mask to match against
with -mvle itself. That flag would also be used for instructions valid in
the VLE mode only (E_* and SE_* mnemonics), that would otherwise never be
enabled.
So for example EVADDW would only be enabled whevener -mvle and -mspe are
used both at the same time, likewise VADDUBS would only work with -mvle
and -maltivec and with a lone -mvle neither of these instructions would be
enabled. The disassembler would work accordingly -- choosing the right
instruction to dump based on the architecture selected or inferred from
ELF object flags and the VLE section attribute.
Maciej
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