[MIPS] Add saa and saad instructions for octeon
Andrew Pinski
andrew.pinski@caviumnetworks.com
Tue Nov 22 04:45:00 GMT 2011
On Thu, Nov 17, 2011 at 11:14 AM, Richard Sandiford
<rdsandiford@googlemail.com> wrote:
> Looks good, subject to Maciej's comments about the tc-mips.c changes.
> Please add tests for some %reloc()s too, once they work.
Here is a new patch which takes into account Maciej's comment about
the tc-mips.c changes. At first I thought it was going to be hard but
there was mostly support for a way different offset (in the
MicroController ASE case of 12bit). This allowed the changes to be
smaller than previous. I also added the testcase for the %lo reloc
just like aclr (the 12bit offset instruction) only tests that reloc
Thanks,
Andrew Pinski
bfd/ChangeLog:
* archures.c (bfd_mach_mips_octeonp): New macro.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c (I_mipsocteonp): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeonp.
* elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
(mips_mach_extensions): Add bfd_mach_mips_octeonp.
gas/ChangeLog:
* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
(NO_ISA_COP): Likewise.
(macro) <ld_st>: Add support when off0 is true.
Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
(mips_cpu_info_table): Add octeon+.
* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=
gas/testsuite/ChangeLog
* gas/mips/mips.exp: Add octeon+ for an architecture.
Run octeon-saa-saad test.
(run_dump_test_arch): For Octeon architectures, also try octeon@.
* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
* gas/mips/octeon.d: Likewise.
* gas/mips/octeon-saa-saad.d: New file.
* gas/mips/octeon-saa-saad.s: New file
include/opcode/ChangeLog:
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
(INSN_OCTEONP): New macro.
(CPU_OCTEONP): New macro.
(OPCODE_IS_MEMBER): Add Octeon+.
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add Octeon+.
* mips-opc.c (IOCT): Include Octeon+.
(IOCTP): New macro.
(mips_builtin_opcodes): Add "saa" and "saad".
-------------- next part --------------
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.160
diff -u -p -r1.160 archures.c
--- bfd/archures.c 2 Nov 2011 03:08:57 -0000 1.160
+++ bfd/archures.c 22 Nov 2011 04:33:49 -0000
@@ -176,6 +176,7 @@ DESCRIPTION
.#define bfd_mach_mips_loongson_3a 3003
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mips_octeon 6501
+.#define bfd_mach_mips_octeonp 6601
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.552
diff -u -p -r1.552 bfd-in2.h
--- bfd/bfd-in2.h 2 Nov 2011 03:08:57 -0000 1.552
+++ bfd/bfd-in2.h 22 Nov 2011 04:33:49 -0000
@@ -1882,6 +1882,7 @@ enum bfd_architecture
#define bfd_mach_mips_loongson_3a 3003
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
+#define bfd_mach_mips_octeonp 6601
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.36
diff -u -p -r1.36 cpu-mips.c
--- bfd/cpu-mips.c 24 Jul 2011 14:20:05 -0000 1.36
+++ bfd/cpu-mips.c 22 Nov 2011 04:33:49 -0000
@@ -93,6 +93,7 @@ enum
I_loongson_2f,
I_loongson_3a,
I_mipsocteon,
+ I_mipsocteonp,
I_xlr,
I_micromips
};
@@ -134,6 +135,7 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
+ N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
};
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.295
diff -u -p -r1.295 elfxx-mips.c
--- bfd/elfxx-mips.c 15 Nov 2011 03:23:56 -0000 1.295
+++ bfd/elfxx-mips.c 22 Nov 2011 04:33:49 -0000
@@ -10885,6 +10885,7 @@ mips_set_isa_flags (bfd *abfd)
break;
case bfd_mach_mips_octeon:
+ case bfd_mach_mips_octeonp:
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
break;
@@ -13491,6 +13492,7 @@ struct mips_mach_extension {
static const struct mips_mach_extension mips_mach_extensions[] = {
/* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
/* MIPS64 extensions. */
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.498
diff -u -p -r1.498 tc-mips.c
--- gas/config/tc-mips.c 16 Nov 2011 12:34:33 -0000 1.498
+++ gas/config/tc-mips.c 22 Nov 2011 04:33:49 -0000
@@ -497,13 +497,16 @@ static int mips_32bitmode = 0;
/* True if CPU has a ror instruction. */
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
+/* True if CPU is in the Octeon family */
+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP)
+
/* True if CPU has seq/sne and seqi/snei instructions. */
-#define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
+#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
/* True if CPU does not implement the all the coprocessor insns. For these
CPUs only those COP insns are accepted that are explicitly marked to be
available on the CPU. ISA membership for COP insns is ignored. */
-#define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
+#define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
@@ -6261,6 +6264,7 @@ macro (struct mips_cl_insn *ip)
int ust = 0;
int lp = 0;
int ab = 0;
+ int off0 = 0;
int off;
offsetT maxnum;
bfd_reloc_code_real_type r;
@@ -8295,20 +8299,29 @@ macro (struct mips_cl_insn *ip)
tempreg, tempreg, breg);
breg = tempreg;
}
- if (!off12)
+ if (off0)
+ {
+ if (offset_expr.X_add_number == 0)
+ tempreg = breg;
+ else
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN,
+ "t,r,j", tempreg, breg, BFD_RELOC_LO16);
+ macro_build (NULL, s, fmt, treg, tempreg);
+ }
+ else if (!off12)
macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s, fmt,
treg, (unsigned long) offset_expr.X_add_number, breg);
}
- else if (off12)
+ else if (off12 || off0)
{
- /* A 12-bit offset field is too narrow to be used for a low-part
- relocation, so load the whole address into the auxillary
- register. In the case of "A(b)" addresses, we first load
- absolute address "A" into the register and then add base
- register "b". In the case of "o(b)" addresses, we simply
- need to add 16-bit offset "o" to base register "b", and
+ /* A 12-bit or 0-bit offset field is too narrow to be used
+ for a low-part relocation, so load the whole address into
+ the auxillary register. In the case of "A(b)" addresses,
+ we first load absolute address "A" into the register and
+ then add base register "b". In the case of "o(b)" addresses,
+ we simply need to add 16-bit offset "o" to base register "b", and
offset_reloc already contains the relocations associated
with "o". */
if (ab)
@@ -8323,8 +8336,11 @@ macro (struct mips_cl_insn *ip)
tempreg, breg, -1,
offset_reloc[0], offset_reloc[1], offset_reloc[2]);
expr1.X_add_number = 0;
- macro_build (NULL, s, fmt,
- treg, (unsigned long) expr1.X_add_number, tempreg);
+ if (off0)
+ macro_build (NULL, s, fmt, treg, tempreg);
+ else
+ macro_build (NULL, s, fmt,
+ treg, (unsigned long) expr1.X_add_number, tempreg);
}
else if (mips_pic == NO_PIC)
{
@@ -9118,6 +9134,22 @@ macro (struct mips_cl_insn *ip)
}
break;
+
+ case M_SAA_AB:
+ ab = 1;
+ case M_SAA_OB:
+ s = "saa";
+ off0 = 1;
+ fmt = "t,(b)";
+ goto ld_st;
+ case M_SAAD_AB:
+ ab = 1;
+ case M_SAAD_OB:
+ s = "saad";
+ off0 = 1;
+ fmt = "t,(b)";
+ goto ld_st;
+
/* New code added to support COPZ instructions.
This code builds table entries out of the macros in mip_opcodes.
R4000 uses interlocks to handle coproc delays.
@@ -19042,6 +19074,7 @@ static const struct mips_cpu_info mips_c
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
+ { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
/* RMI Xlr */
{ "xlr", 0, ISA_MIPS64, CPU_XLR },
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.62
diff -u -p -r1.62 c-mips.texi
--- gas/doc/c-mips.texi 16 Nov 2011 12:21:35 -0000 1.62
+++ gas/doc/c-mips.texi 22 Nov 2011 04:33:49 -0000
@@ -323,6 +323,7 @@ loongson2e,
loongson2f,
loongson3a,
octeon,
+octeon+,
xlr
@end quotation
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.194
diff -u -p -r1.194 mips.exp
--- gas/testsuite/gas/mips/mips.exp 21 Nov 2011 11:18:28 -0000 1.194
+++ gas/testsuite/gas/mips/mips.exp 22 Nov 2011 04:33:50 -0000
@@ -308,7 +308,13 @@ proc run_dump_test_arch { name arch } {
set format [expr { $elf ? "elf" : $ecoff ? "ecoff" : "aout" }]
set proparch [lindex [mips_arch_properties $arch 0] 0]
- foreach prefix [list ${proparch}@${format}@ ${proparch}@ ${format}@] {
+ set prefixes [list ${proparch}@${format}@ ${proparch}@ ]
+ if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
+ lappend prefixes octeon@
+ lappend prefixes octeon@${format}@
+ }
+ lappend prefixes ${format}@
+ foreach prefix ${prefixes} {
set archname ${prefix}${name}
if { [file exists "$srcdir/$subdir/${archname}.d"] } {
set name $archname
@@ -412,6 +418,9 @@ mips_arch_create sb1 64 mips64 { mips3d
mips_arch_create octeon 64 mips64r2 {} \
{ -march=octeon -mtune=octeon } { -mmips:octeon } \
{ mips64octeon*-*-* }
+mips_arch_create octeonp 64 octeon {} \
+ { -march=octeon+ -mtune=octeon+ } { -mmips:octeon+ } \
+ { }
mips_arch_create xlr 64 mips64 {} \
{ -march=xlr -mtune=xlr } { -mmips:xlr }
@@ -981,6 +990,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "loongson-3a-3"
run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
+ run_dump_test_arches "octeon-saa-saad" [mips_arch_list_matching octeonp]
run_list_test_arches "octeon-ill" "" \
[mips_arch_list_matching octeon]
run_dump_test_arches "octeon-pref" [mips_arch_list_matching octeon]
Index: gas/testsuite/gas/mips/octeon-pref.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/octeon-pref.d,v
retrieving revision 1.1
diff -u -p -r1.1 octeon-pref.d
--- gas/testsuite/gas/mips/octeon-pref.d 4 Oct 2010 15:24:49 -0000 1.1
+++ gas/testsuite/gas/mips/octeon-pref.d 22 Nov 2011 04:33:50 -0000
@@ -1,4 +1,4 @@
-#as: -march=octeon -64 -mfix-cn63xxp1
+#as: -64 -mfix-cn63xxp1
#objdump: -M reg-names=numeric -dr
#name: MIPS octeon-pref mfix-cn63xxp1
Index: gas/testsuite/gas/mips/octeon-saa-saad.d
===================================================================
RCS file: gas/testsuite/gas/mips/octeon-saa-saad.d
diff -N gas/testsuite/gas/mips/octeon-saa-saad.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/octeon-saa-saad.d 22 Nov 2011 04:33:50 -0000
@@ -0,0 +1,58 @@
+#objdump: -d -r --show-raw-insn
+#name: MIPS-OCTEON octeon_saa_saad
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*: 70450018 saa a1,\(v0\)
+.*: 70860019 saad a2,\(a0\)
+.*: 00000000 nop
+.*: 70450018 saa a1,\(v0\)
+.*: 70860019 saad a2,\(a0\)
+.*: 00000000 nop
+.*: 3c010000 lui at,0x0
+ 18: R_MIPS_HI16 .text
+.*: 24210000 addiu at,at,0
+ 1c: R_MIPS_LO16 .text
+.*: 70250018 saa a1,\(at\)
+.*: 3c010000 lui at,0x0
+ 24: R_MIPS_HI16 .text
+.*: 24210000 addiu at,at,0
+ 28: R_MIPS_LO16 .text
+.*: 70220019 saad v0,\(at\)
+.*: 00000000 nop
+.*: 3c011234 lui at,0x1234
+.*: 24215678 addiu at,at,22136
+.*: 70240018 saa a0,\(at\)
+.*: 3c011234 lui at,0x1234
+.*: 24215678 addiu at,at,22136
+.*: 70240019 saad a0,\(at\)
+.*: 00000000 nop
+.*: 24811234 addiu at,a0,4660
+.*: 70250018 saa a1,\(at\)
+.*: 2401003c li at,60
+.*: 70260019 saad a2,\(at\)
+.*: 00000000 nop
+.*: 3c010012 lui at,0x12
+.*: 00240821 addu at,at,a0
+.*: 24213456 addiu at,at,13398
+.*: 70250018 saa a1,\(at\)
+.*: 24c11234 addiu at,a2,4660
+.*: 70260018 saa a2,\(at\)
+.*: 00000000 nop
+.*: 24a15678 addiu at,a1,22136
+.*: 70240019 saad a0,\(at\)
+.*: 3c010056 lui at,0x56
+.*: 00250821 addu at,at,a1
+.*: 24217891 addiu at,at,30865
+.*: 70250019 saad a1,\(at\)
+.*: 00000000 nop
+.*: 24a10000 addiu at,a1,0
+ 9c: R_MIPS_LO16 .text
+.*: 70240018 saa a0,\(at\)
+.*: 24a10000 addiu at,a1,0
+ a4: R_MIPS_LO16 .text
+.*: 70240019 saad a0,\(at\)
+.*: 00000000 nop
Index: gas/testsuite/gas/mips/octeon-saa-saad.s
===================================================================
RCS file: gas/testsuite/gas/mips/octeon-saa-saad.s
diff -N gas/testsuite/gas/mips/octeon-saa-saad.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/octeon-saa-saad.s 22 Nov 2011 04:33:50 -0000
@@ -0,0 +1,33 @@
+ .text
+foo:
+ saa $5,($2)
+ saad $6,($4)
+ nop
+
+ saa $5,0($2)
+ saad $6,0($4)
+ nop
+
+ saa $5, foo
+ saad $2, foo
+ nop
+
+ saa $4, 0x12345678
+ saad $4, 0x12345678
+ nop
+
+ saa $5, 0x1234($4)
+ saad $6, 60($0)
+ nop
+
+ saa $5, 0x123456($4)
+ saa $6, 0x1234($6)
+ nop
+
+ saad $4, 0x5678($5)
+ saad $5, 0x567891($5)
+ nop
+
+ saa $4, %lo(foo)($5)
+ saad $4, %lo(foo)($5)
+ nop
Index: gas/testsuite/gas/mips/octeon.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/octeon.d,v
retrieving revision 1.6
diff -u -p -r1.6 octeon.d
--- gas/testsuite/gas/mips/octeon.d 18 Feb 2009 20:51:59 -0000 1.6
+++ gas/testsuite/gas/mips/octeon.d 22 Nov 2011 04:33:50 -0000
@@ -1,4 +1,4 @@
-#as: -march=octeon -64
+#as: -64
#objdump: -M reg-names=numeric -dr
#name: MIPS octeon instructions
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.80
diff -u -p -r1.80 mips.h
--- include/opcode/mips.h 24 Oct 2011 14:21:41 -0000 1.80
+++ include/opcode/mips.h 22 Nov 2011 04:33:50 -0000
@@ -713,10 +713,11 @@ static const unsigned int mips_isa_table
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0c20
+#define INSN_CHIP_MASK 0xc3ff0e20
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
+#define INSN_OCTEONP 0x00000200
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f010
@@ -823,6 +824,7 @@ static const unsigned int mips_isa_table
#define CPU_LOONGSON_2F 3002
#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
+#define CPU_OCTEONP 6601
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Test for membership in an ISA including chip specific ISAs. INSN
@@ -859,6 +861,8 @@ static const unsigned int mips_isa_table
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
+ || (cpu == CPU_OCTEONP \
+ && ((insn)->membership & INSN_OCTEONP) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
@@ -1065,6 +1069,10 @@ enum
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SAA_AB,
+ M_SAA_OB,
+ M_SAAD_AB,
+ M_SAAD_OB,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.86
diff -u -p -r1.86 mips-dis.c
--- opcodes/mips-dis.c 9 Aug 2011 15:20:03 -0000 1.86
+++ opcodes/mips-dis.c 22 Nov 2011 04:33:50 -0000
@@ -605,6 +605,10 @@ const struct mips_arch_choice mips_arch_
ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
mips_hwr_names_numeric },
+ { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
+ ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEONP, mips_cp0_names_numeric,
+ NULL, 0, mips_hwr_names_numeric },
+
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR,
mips_cp0_names_xlr,
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.88
diff -u -p -r1.88 mips-opc.c
--- opcodes/mips-opc.c 9 Aug 2011 15:20:03 -0000 1.88
+++ opcodes/mips-opc.c 22 Nov 2011 04:33:51 -0000
@@ -121,7 +121,8 @@
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
-#define IOCT INSN_OCTEON
+#define IOCT (INSN_OCTEON | INSN_OCTEONP)
+#define IOCTP INSN_OCTEONP
#define XLR INSN_XLR
#define G1 (T3 \
@@ -1247,6 +1248,12 @@ const struct mips_opcode mips_builtin_op
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
+{"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP },
+{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP },
+{"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
+{"saad", "t,o(b)", 0, (int) M_SAAD_OB, INSN_MACRO, 0, IOCTP },
+{"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP },
+{"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
More information about the Binutils
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