[PATCH 2/3] sparc: Change software trap amd mov handling
Mark Fortescue
mark@mtfhpc.demon.co.uk
Sat Aug 27 00:06:00 GMT 2011
Hi all,
Please find attached a patch to change the software trap and mov
instruction handling into line with the V8 SPARC Architecture Manual.
wr instructions are also updated to match the changes to the mov
instructions.
The V8 manual has an extra software_tarp# mode not handled by gas:
imm7 + regrs1
Synthetic instruction changes:
GAS uses 'wr regrs1, %g0, regrd' and 'wr %g0, imm, regrd'
for 'mov imm_reg, regrd'.
The V8 manual uses 'wr %g0, imm_regrs2, regrd'
for 'mov imm_reg, regrd'.
Change the behaviour to match the V8 manual.
Regards
Mark Fortescue.
PS: Sorry the patch is attached. My mail client mangles in-text patches.
-------------- next part --------------
diff -rupN binutils-26Aug2011-cvs.old/gas/testsuite/ChangeLog binutils-26Aug2011-cvs/gas/testsuite/ChangeLog
--- binutils-26Aug2011-cvs.old/gas/testsuite/ChangeLog 2011-08-19 20:27:52.000000000 +0100
+++ binutils-26Aug2011-cvs/gas/testsuite/ChangeLog 2011-08-26 21:00:26.000000000 +0100
@@ -1,3 +1,9 @@
+2011-08-26 Mark Fortescue <mark@mtfhpc.demon.co.uk>
+
+ * gas/sparc/ticc-imm-reg.[sd]: New test.
+ * gas/sparc/v8-movwr-imm.[sd]: New test.
+ * gas/sparc/sparc.exp: Run new tests.
+
2011-08-26 Mark Fortescue <mark@mtfhpc.demon.co.uk>
* gas/sparc/imm-plus-rreg.[sd]: New test.
diff -rupN binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/sparc.exp binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/sparc.exp
--- binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/sparc.exp 2011-08-05 17:52:48.000000000 +0100
+++ binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/sparc.exp 2011-08-26 20:19:29.000000000 +0100
@@ -51,6 +51,8 @@ if [istarget sparc*-*-*] {
run_dump_test "gotop64"
}
run_dump_test "imm-plus-rreg"
+ run_dump_test "ticc-imm-reg"
+ run_dump_test "v8-movwr-imm"
run_dump_test "v9branch1"
run_dump_test "v9branch2"
run_dump_test "v9branch3"
diff -rupN binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/v8-movwr-imm.d binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/v8-movwr-imm.d
--- binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/v8-movwr-imm.d 1970-01-01 01:00:00.000000000 +0100
+++ binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/v8-movwr-imm.d 2011-08-26 16:57:17.000000000 +0100
@@ -0,0 +1,49 @@
+#as: -Av8
+#objdump: -dr
+#name: V8 mov/wr aliases
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <foo>:
+ 0: 83 80 00 10 mov %l0, %asr1
+ 4: 81 80 00 10 mov %l0, %y
+ 8: 81 88 00 10 mov %l0, %psr
+ c: 81 90 00 10 mov %l0, %wim
+ 10: 81 98 00 10 mov %l0, %tbr
+ 14: 83 80 00 00 mov %g0, %asr1
+ 18: 81 80 00 00 mov %g0, %y
+ 1c: 81 88 00 00 mov %g0, %psr
+ 20: 81 90 00 00 mov %g0, %wim
+ 24: 81 98 00 00 mov %g0, %tbr
+ 28: 83 80 20 00 mov %g0, %asr1
+ 2c: 81 80 20 00 mov %g0, %y
+ 30: 81 88 20 00 mov %g0, %psr
+ 34: 81 90 20 00 mov %g0, %wim
+ 38: 81 98 20 00 mov %g0, %tbr
+ 3c: 83 80 3f ff mov -1, %asr1
+ 40: 81 80 3f ff mov -1, %y
+ 44: 81 88 3f ff mov -1, %psr
+ 48: 81 90 3f ff mov -1, %wim
+ 4c: 81 98 3f ff mov -1, %tbr
+ 50: 83 80 00 10 mov %l0, %asr1
+ 54: 81 80 00 10 mov %l0, %y
+ 58: 81 88 00 10 mov %l0, %psr
+ 5c: 81 90 00 10 mov %l0, %wim
+ 60: 81 98 00 10 mov %l0, %tbr
+ 64: 83 80 00 00 mov %g0, %asr1
+ 68: 81 80 00 00 mov %g0, %y
+ 6c: 81 88 00 00 mov %g0, %psr
+ 70: 81 90 00 00 mov %g0, %wim
+ 74: 81 98 00 00 mov %g0, %tbr
+ 78: 83 80 20 00 mov %g0, %asr1
+ 7c: 81 80 20 00 mov %g0, %y
+ 80: 81 88 20 00 mov %g0, %psr
+ 84: 81 90 20 00 mov %g0, %wim
+ 88: 81 98 20 00 mov %g0, %tbr
+ 8c: 83 80 3f ff mov -1, %asr1
+ 90: 81 80 3f ff mov -1, %y
+ 94: 81 88 3f ff mov -1, %psr
+ 98: 81 90 3f ff mov -1, %wim
+ 9c: 81 98 3f ff mov -1, %tbr
diff -rupN binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/v8-movwr-imm.s binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/v8-movwr-imm.s
--- binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/v8-movwr-imm.s 1970-01-01 01:00:00.000000000 +0100
+++ binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/v8-movwr-imm.s 2011-08-26 16:55:06.000000000 +0100
@@ -0,0 +1,45 @@
+! Make 'mov' and 'wr' aliases operate as per V8 SPARC Architecture Manual
+ .text
+foo:
+ ! wr Aliases
+ wr %l0,%asr1
+ wr %l0,%y
+ wr %l0,%psr
+ wr %l0,%wim
+ wr %l0,%tbr
+ wr %g0,%asr1
+ wr %g0,%y
+ wr %g0,%psr
+ wr %g0,%wim
+ wr %g0,%tbr
+ wr 0,%asr1
+ wr 0,%y
+ wr 0,%psr
+ wr 0,%wim
+ wr 0,%tbr
+ wr -1,%asr1
+ wr -1,%y
+ wr -1,%psr
+ wr -1,%wim
+ wr -1,%tbr
+ ! mov Aliases
+ mov %l0,%asr1
+ mov %l0,%y
+ mov %l0,%psr
+ mov %l0,%wim
+ mov %l0,%tbr
+ mov %g0,%asr1
+ mov %g0,%y
+ mov %g0,%psr
+ mov %g0,%wim
+ mov %g0,%tbr
+ mov 0,%asr1
+ mov 0,%y
+ mov 0,%psr
+ mov 0,%wim
+ mov 0,%tbr
+ mov -1,%asr1
+ mov -1,%y
+ mov -1,%psr
+ mov -1,%wim
+ mov -1,%tbr
diff -rupN binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/ticc-imm-reg.d binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/ticc-imm-reg.d
--- binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/ticc-imm-reg.d 1970-01-01 01:00:00.000000000 +0100
+++ binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/ticc-imm-reg.d 2011-08-26 15:43:55.000000000 +0100
@@ -0,0 +1,18 @@
+#as: -Av8
+#objdump: -dr
+#name: software traps
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <foo>:
+ 0: 91 d2 00 00 ta %o0
+ 4: 91 d2 00 0a ta %o0 \+ %o2
+ 8: 91 d4 20 0a ta %l0 \+ 0xa
+ c: 91 d4 3f f6 ta %l0 \+ -10
+ 10: 91 d4 3f f6 ta %l0 \+ -10
+ 14: 91 d4 20 0a ta %l0 \+ 0xa
+ 18: 91 d0 20 7f ta 0x7f
+ 1c: 91 d6 20 0a ta %i0 \+ 0xa
+ 20: 91 d6 3f f6 ta %i0 \+ -10
diff -rupN binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/ticc-imm-reg.s binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/ticc-imm-reg.s
--- binutils-26Aug2011-cvs.old/gas/testsuite/gas/sparc/ticc-imm-reg.s 1970-01-01 01:00:00.000000000 +0100
+++ binutils-26Aug2011-cvs/gas/testsuite/gas/sparc/ticc-imm-reg.s 2011-08-26 15:08:05.000000000 +0100
@@ -0,0 +1,12 @@
+! Make ticc aliases operate as per V8 SPARC Architecture Manual
+ .text
+foo:
+ ta %o0
+ ta %o0 + %o2
+ ta %l0 + 10
+ ta %l0 + -10
+ ta %l0 - 10
+ ta %l0 - -10
+ ta 127
+ ta 10 + %i0
+ ta -10 + %i0
diff -rupN binutils-26Aug2011-cvs.old/opcodes/ChangeLog binutils-26Aug2011-cvs/opcodes/ChangeLog
--- binutils-26Aug2011-cvs.old/opcodes/ChangeLog 2011-08-22 16:25:05.000000000 +0100
+++ binutils-26Aug2011-cvs/opcodes/ChangeLog 2011-08-26 20:56:43.000000000 +0100
@@ -1,3 +1,17 @@
+2011-08-26 Mark Fortescue <mark@mtfhpc.demon.co.uk>
+
+ The changes below bring 'mov' and 'ticc' instructions into line
+ with the V8 SPARC Architecture Manual.
+ * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
+ * sparc-opc.c (sparc_opcodes): Add alias entries for
+ 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
+ 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
+ * sparc-opc.c (sparc_opcodes): Move/Change entries for
+ 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
+ and 'mov imm,%tbr'.
+ * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
+ mov aliases.
+
2011-08-22 Nick Clifton <nickc@redhat.com>
* Makefile.am (CPUDIR): Redfine to point to top level cpu
diff -rupN binutils-26Aug2011-cvs.old/opcodes/sparc-opc.c binutils-26Aug2011-cvs/opcodes/sparc-opc.c
--- binutils-26Aug2011-cvs.old/opcodes/sparc-opc.c 2011-08-26 13:57:34.000000000 +0100
+++ binutils-26Aug2011-cvs/opcodes/sparc-opc.c 2011-08-26 16:02:59.000000000 +0100
@@ -820,18 +820,28 @@ const struct sparc_opcode sparc_opcodes[
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */
+{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, v8 }, /* wr %g0,rs2,%asrX */
+{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */
+{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, v6 }, /* wr %g0,rs2,%y */
+{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
+{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, v6notv9 }, /* wr %g0,rs2,%psr */
+{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
+{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, v6notv9 }, /* wr %g0,rs2,%wim */
+{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
+{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, v6notv9 }, /* wr %g0,rs2,%tbr */
+{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
@@ -918,20 +928,25 @@ const struct sparc_opcode sparc_opcodes[
{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
+{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, v8 }, /* wr %g0,rs2,%asrX */
+{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
-{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
+{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, v6 }, /* wr %g0,rs2,%y */
+{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
-{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
+{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, v6notv9 }, /* wr %g0,rs2,%psr */
+{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
-{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
+{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, v6notv9 }, /* wr %g0,rs2,%wim */
+{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
-{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
+{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, v6notv9 }, /* wr %g0,rs2,%tbr */
+{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
-{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */
@@ -1107,6 +1122,7 @@ const struct sparc_opcode sparc_opcodes[
{ opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
{ opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
{ opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
+ { opcode, (mask)|IMMED, (lose), "i+1", (flags), v6 }, /* imm + rs1 */ \
{ opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
{ opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
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