[vms/committed]: generate and write the GST

[h.becker]

Tristan Gingold wrote:

> I agree that the GST is not required and that the DST should be enough.  *But* I was unable to
> use debug with files without GST, hence my comment.
I don't know what you saw. Was there a debugger error message? If you 
compile /debug and link /nodebug you can still "run/debug" and the 
debugger shows the variables etc. Then there is DST but no GST in the image.

>>> --- 1632,1639 ----
>>>          return RELC_SHR_BASE + PRIV2 (h->sym->owner, shr_index);
>>>        else
>>>          {
>>> !           /* Can this happen (non-relocatable symg) ?  I'd like to see
>>> !              an example.  */
>>>            abort ();
>>>          }
>>>      }
>> An EGSD$C_SYMG with EGSY$V_REL==0? Easily:
>> $ cre x.mar
>> whatever==4711
>> .end
>> $ mac x
>> $ link x/share,tt:/opt
>> symbol_v=(whatever=data)
>> ^Z
>> $
> 
> Right, but is it different from a REL symbol, given that the section is an absolute section ?
> What is the meaning of the REL flag for SYMG ?

As you probably know, the REL symbol is relocatable. For a GST, which 
usually contains the universal symbols, it means that the corresponding 
symbol vector entry contains an address, not a constant value.

Hartmut