[PATCH] powerpc: ignore opcodes on e500/SPE which can't be mixed

Sebastian Andrzej Siewior binutils@ml.breakpoint.cc
Sun May 2 13:42:00 GMT 2010


This is a set of 3 three patches merged into one which marks certain
opcodes invalid if the assembler is started with -me500 which inveherits
SPE and EFS.
It happend often in the past, that a application sneaks in some opcodes
which don't belong in there. This is often the result of developers that
assume that a powerpc has always the FPU unit which is not the case on
e500.
This makes sure that those opcodes can't be assembled in e500 mode.
This is not the fault of the compiler as the opcodes sneak in via .S
files or asm("bla").

I have the three patches which I mixed into one also as three seperate,
if this is the prefered way.

powerpc: VMX opcodes are not supported by if using the SPE

VMX are not supported by the e500 core based CPUs which use SPE for vector
operations. Some of the opcodes share the same range. This ensures that the
assembler bails out if it sees such an opcode.

Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>

powerpc: Don't use floating point together with embedded floating point

the e500 cores use embedded floating point instead of "traditional" floating
point. The usage of floating point opcodes results in an invalid opcode. This
ensures the compiler bails out early. All opcodes which touch floating
point registers are marked.

Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>

powerpc: Ignore lwsync on if using SPE

the e500 cores, which are the only user of the SPE opcodes, don't recognize
the lwsync opcode. Using it results in an invalid opcode. This ensures that
the assembler bails out early instead of assembling.

Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>

---
 opcodes/ChangeLog |    6 +
 opcodes/ppc-opc.c |  986 ++++++++++++++++++++++++++--------------------------
 2 files changed, 499 insertions(+), 493 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6e50e03..9c2d3d0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2010-05-02  Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+
+	* ppc-opcodes.c: Deprecate all PPCVEC opcodes on PPCSPE,
+	deprecate opcodes which use floating point registers on PPCEFS,
+	deprecate lwsync on PPCSPE.
+
 2010-04-22  Nick Clifton  <nickc@redhat.com>
 
 	* po/opcodes.pot: Updated by the Translation project.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 3cad939..23aba19 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2013,170 +2013,170 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"twi",		OP(3),		OP_MASK,     PPCCOM,	PPCNONE,	{TO, RA, SI}},
 {"ti",		OP(3),		OP_MASK,     PWRCOM,	PPCNONE,	{TO, RA, SI}},
 
-{"ps_cmpu0",	X  (4,	 0), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
-{"vaddubm",	VX (4,	 0),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmaxub",	VX (4,	 2),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vrlb",	VX (4,	 4),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpequb",	VXR(4,	 6,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmuloub",	VX (4,	 8),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vaddfp",	VX (4,	10),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"psq_lx",	XW (4,	 6,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRT,RA,RB,PSWM,PSQM}},
-{"vmrghb",	VX (4,	12),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRS,RA,RB,PSWM,PSQM}},
-{"vpkuhum",	VX (4,	14),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"ps_cmpu0",	X  (4,	 0), X_MASK|(3<<21), PPCPS,	PPCEFS,		{BF, FRA, FRB}},
+{"vaddubm",	VX (4,	 0),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmaxub",	VX (4,	 2),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vrlb",	VX (4,	 4),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpequb",	VXR(4,	 6,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmuloub",	VX (4,	 8),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vaddfp",	VX (4,	10),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"psq_lx",	XW (4,	 6,0),	XW_MASK,     PPCPS,	PPCEFS,		{FRT,RA,RB,PSWM,PSQM}},
+{"vmrghb",	VX (4,	12),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	PPCEFS,		{FRS,RA,RB,PSWM,PSQM}},
+{"vpkuhum",	VX (4,	14),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"mulhhwu",	XRC(4,	 8,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"mulhhwu.",	XRC(4,	 8,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
-{"ps_sum0",	A  (4,	10,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_sum0.",	A  (4,	10,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_sum1",	A  (4,	11,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_sum1.",	A  (4,	11,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"ps_sum0",	A  (4,	10,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_sum0.",	A  (4,	10,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_sum1",	A  (4,	11,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_sum1.",	A  (4,	11,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 {"ps_muls0",	A  (4,	12,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
 {"machhwu",	XO (4,	12,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_muls0.",	A  (4,	12,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
+{"ps_muls0.",	A  (4,	12,1),	AFRB_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRC}},
 {"machhwu.",	XO (4,	12,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_muls1",	A  (4,	13,0),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"ps_muls1.",	A  (4,	13,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"ps_madds0",	A  (4,	14,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_madds0.",	A  (4,	14,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_madds1",	A  (4,	15,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_madds1.",	A  (4,	15,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"vmhaddshs",	VXA(4,	32),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"vmhraddshs",	VXA(4,	33),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"vmladduhm",	VXA(4,	34),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"ps_div",	A  (4,	18,0),	AFRC_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"vmsumubm",	VXA(4,	36),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"ps_div.",	A  (4,	18,1),	AFRC_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"vmsummbm",	VXA(4,	37),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"vmsumuhm",	VXA(4,	38),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"vmsumuhs",	VXA(4,	39),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"ps_sub",	A  (4,	20,0),	AFRC_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"vmsumshm",	VXA(4,	40),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"ps_sub.",	A  (4,	20,1),	AFRC_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"vmsumshs",	VXA(4,	41),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"ps_add",	A  (4,	21,0),	AFRC_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"vsel",	VXA(4,	42),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"ps_add.",	A  (4,	21,1),	AFRC_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"vperm",	VXA(4,	43),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, VC}},
-{"vsldoi",	VXA(4,	44),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB, SHB}},
-{"ps_sel",	A  (4,	23,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"vmaddfp",	VXA(4,	46),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VC, VB}},
-{"ps_sel.",	A  (4,	23,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"vnmsubfp",	VXA(4,	47),	VXA_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VC, VB}},
-{"ps_res",	A  (4,	24,0), AFRAFRC_MASK, PPCPS,	PPCNONE,	{FRT, FRB}},
-{"ps_res.",	A  (4,	24,1), AFRAFRC_MASK, PPCPS,	PPCNONE,	{FRT, FRB}},
-{"ps_mul",	A  (4,	25,0), AFRB_MASK,    PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"ps_mul.",	A  (4,	25,1),	AFRB_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRC}},
-{"ps_rsqrte",	A  (4,	26,0), AFRAFRC_MASK, PPCPS,	PPCNONE,	{FRT, FRB}},
-{"ps_rsqrte.",	A  (4,	26,1), AFRAFRC_MASK, PPCPS,	PPCNONE,	{FRT, FRB}},
-{"ps_msub",	A  (4,	28,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_msub.",	A  (4,	28,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_madd",	A  (4,	29,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_madd.",	A  (4,	29,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_nmsub",	A  (4,	30,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_nmsub.",	A  (4,	30,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_nmadd",	A  (4,	31,0),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_nmadd.",	A  (4,	31,1),	A_MASK,      PPCPS,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"ps_cmpo0",	X  (4,	32), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
-{"vadduhm",	VX (4,	64),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmaxuh",	VX (4,	66),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vrlh",	VX (4,	68),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpequh",	VXR(4,	70,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmulouh",	VX (4,	72),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vsubfp",	VX (4,	74),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"psq_lux",	XW (4,	38,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRT,RA,RB,PSWM,PSQM}},
-{"vmrghh",	VX (4,	76),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	PPCNONE,	{FRS,RA,RB,PSWM,PSQM}},
-{"vpkuwum",	VX (4,	78),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"ps_neg",	XRC(4,	40,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
+{"ps_muls1",	A  (4,	13,0),	AFRB_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRC}},
+{"ps_muls1.",	A  (4,	13,1),	AFRB_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRC}},
+{"ps_madds0",	A  (4,	14,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_madds0.",	A  (4,	14,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_madds1",	A  (4,	15,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_madds1.",	A  (4,	15,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"vmhaddshs",	VXA(4,	32),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"vmhraddshs",	VXA(4,	33),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"vmladduhm",	VXA(4,	34),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"ps_div",	A  (4,	18,0),	AFRC_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"vmsumubm",	VXA(4,	36),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"ps_div.",	A  (4,	18,1),	AFRC_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"vmsummbm",	VXA(4,	37),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"vmsumuhm",	VXA(4,	38),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"vmsumuhs",	VXA(4,	39),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"ps_sub",	A  (4,	20,0),	AFRC_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"vmsumshm",	VXA(4,	40),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"ps_sub.",	A  (4,	20,1),	AFRC_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"vmsumshs",	VXA(4,	41),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"ps_add",	A  (4,	21,0),	AFRC_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"vsel",	VXA(4,	42),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"ps_add.",	A  (4,	21,1),	AFRC_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"vperm",	VXA(4,	43),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, VC}},
+{"vsldoi",	VXA(4,	44),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB, SHB}},
+{"ps_sel",	A  (4,	23,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"vmaddfp",	VXA(4,	46),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VC, VB}},
+{"ps_sel.",	A  (4,	23,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"vnmsubfp",	VXA(4,	47),	VXA_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VC, VB}},
+{"ps_res",	A  (4,	24,0), AFRAFRC_MASK, PPCPS,	PPCEFS,		{FRT, FRB}},
+{"ps_res.",	A  (4,	24,1), AFRAFRC_MASK, PPCPS,	PPCEFS,		{FRT, FRB}},
+{"ps_mul",	A  (4,	25,0), AFRB_MASK,    PPCPS,	PPCEFS,		{FRT, FRA, FRC}},
+{"ps_mul.",	A  (4,	25,1),	AFRB_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRC}},
+{"ps_rsqrte",	A  (4,	26,0), AFRAFRC_MASK, PPCPS,	PPCEFS,		{FRT, FRB}},
+{"ps_rsqrte.",	A  (4,	26,1), AFRAFRC_MASK, PPCPS,	PPCEFS,		{FRT, FRB}},
+{"ps_msub",	A  (4,	28,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_msub.",	A  (4,	28,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_madd",	A  (4,	29,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_madd.",	A  (4,	29,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_nmsub",	A  (4,	30,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_nmsub.",	A  (4,	30,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_nmadd",	A  (4,	31,0),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_nmadd.",	A  (4,	31,1),	A_MASK,      PPCPS,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"ps_cmpo0",	X  (4,	32), X_MASK|(3<<21), PPCPS,	PPCEFS,		{BF, FRA, FRB}},
+{"vadduhm",	VX (4,	64),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmaxuh",	VX (4,	66),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vrlh",	VX (4,	68),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpequh",	VXR(4,	70,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmulouh",	VX (4,	72),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vsubfp",	VX (4,	74),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"psq_lux",	XW (4,	38,0),	XW_MASK,     PPCPS,	PPCEFS,		{FRT,RA,RB,PSWM,PSQM}},
+{"vmrghh",	VX (4,	76),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	PPCEFS,		{FRS,RA,RB,PSWM,PSQM}},
+{"vpkuwum",	VX (4,	78),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"ps_neg",	XRC(4,	40,0),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
 {"mulhhw",	XRC(4,	40,0),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
-{"ps_neg.",	XRC(4,	40,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
+{"ps_neg.",	XRC(4,	40,1),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
 {"mulhhw.",	XRC(4,	40,1),	X_MASK,      MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"machhw",	XO (4,	44,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"machhw.",	XO (4,	44,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"nmachhw",	XO (4,	46,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"nmachhw.",	XO (4,	46,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
-{"ps_cmpu1",	X  (4,	64), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
-{"vadduwm",	VX (4,	128),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmaxuw",	VX (4,	130),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vrlw",	VX (4,	132),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpequw",	VXR(4,	134,0), VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmrghw",	VX (4,	140),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vpkuhus",	VX (4,	142),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"ps_mr",	XRC(4,	72,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"ps_mr.",	XRC(4,	72,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
+{"ps_cmpu1",	X  (4,	64), X_MASK|(3<<21), PPCPS,	PPCEFS,		{BF, FRA, FRB}},
+{"vadduwm",	VX (4,	128),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmaxuw",	VX (4,	130),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vrlw",	VX (4,	132),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpequw",	VXR(4,	134,0), VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmrghw",	VX (4,	140),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vpkuhus",	VX (4,	142),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"ps_mr",	XRC(4,	72,0),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
+{"ps_mr.",	XRC(4,	72,1),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
 {"machhwsu",	XO (4,	76,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"machhwsu.",	XO (4,	76,0,1),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
-{"ps_cmpo1",	X  (4,	96), X_MASK|(3<<21), PPCPS,	PPCNONE,	{BF, FRA, FRB}},
-{"vcmpeqfp",	VXR(4, 198,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vpkuwus",	VX (4, 206),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"ps_cmpo1",	X  (4,	96), X_MASK|(3<<21), PPCPS,	PPCEFS,		{BF, FRA, FRB}},
+{"vcmpeqfp",	VXR(4, 198,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vpkuwus",	VX (4, 206),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"machhws",	XO (4, 108,0,0),XO_MASK,     MULHW, 	PPCNONE,	{RT, RA, RB}},
 {"machhws.",	XO (4, 108,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmachhws",	XO (4, 110,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmachhws.",	XO (4, 110,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vmaxsb",	VX (4, 258),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vslb",	VX (4, 260),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmulosb",	VX (4, 264),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vrefp",	VX (4, 266),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"vmrglb",	VX (4, 268),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vpkshus",	VX (4, 270),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"ps_nabs",	XRC(4, 136,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
+{"vmaxsb",	VX (4, 258),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vslb",	VX (4, 260),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmulosb",	VX (4, 264),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vrefp",	VX (4, 266),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
+{"vmrglb",	VX (4, 268),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vpkshus",	VX (4, 270),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"ps_nabs",	XRC(4, 136,0),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
 {"mulchwu",	XRC(4, 136,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_nabs.",	XRC(4, 136,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
+{"ps_nabs.",	XRC(4, 136,1),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
 {"mulchwu.",	XRC(4, 136,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"macchwu",	XO (4, 140,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"macchwu.",	XO (4, 140,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vmaxsh",	VX (4, 322),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vslh",	VX (4, 324),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmulosh",	VX (4, 328),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vrsqrtefp",	VX (4, 330),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"vmrglh",	VX (4, 332),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vpkswus",	VX (4, 334),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vmaxsh",	VX (4, 322),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vslh",	VX (4, 324),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmulosh",	VX (4, 328),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vrsqrtefp",	VX (4, 330),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
+{"vmrglh",	VX (4, 332),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vpkswus",	VX (4, 334),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"mulchw",	XRC(4, 168,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"mulchw.",	XRC(4, 168,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"macchw",	XO (4, 172,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"macchw.",	XO (4, 172,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmacchw",	XO (4, 174,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmacchw.",	XO (4, 174,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vaddcuw",	VX (4, 384),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmaxsw",	VX (4, 386),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vslw",	VX (4, 388),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vexptefp",	VX (4, 394),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"vmrglw",	VX (4, 396),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vpkshss",	VX (4, 398),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vaddcuw",	VX (4, 384),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmaxsw",	VX (4, 386),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vslw",	VX (4, 388),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vexptefp",	VX (4, 394),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
+{"vmrglw",	VX (4, 396),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vpkshss",	VX (4, 398),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"macchwsu",	XO (4, 204,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"macchwsu.",	XO (4, 204,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vsl",		VX (4, 452),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgefp",	VXR(4, 454,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vlogefp",	VX (4, 458),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"vpkswss",	VX (4, 462),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsl",		VX (4, 452),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgefp",	VXR(4, 454,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vlogefp",	VX (4, 458),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
+{"vpkswss",	VX (4, 462),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"macchws",	XO (4, 236,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"macchws.",	XO (4, 236,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmacchws",	XO (4, 238,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmacchws.",	XO (4, 238,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evaddw",	VX (4, 512),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vaddubs",	VX (4, 512),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vaddubs",	VX (4, 512),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evaddiw",	VX (4, 514),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB, UIMM}},
-{"vminub",	VX (4, 514),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vminub",	VX (4, 514),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evsubfw",	VX (4, 516),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evsubw",	VX (4, 516),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB, RA}},
-{"vsrb",	VX (4, 516),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsrb",	VX (4, 516),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evsubifw",	VX (4, 518),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, UIMM, RB}},
 {"evsubiw",	VX (4, 518),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB, UIMM}},
-{"vcmpgtub",	VXR(4, 518,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpgtub",	VXR(4, 518,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evabs",	VX (4, 520),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vmuleub",	VX (4, 520),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vmuleub",	VX (4, 520),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evneg",	VX (4, 521),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evextsb",	VX (4, 522),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vrfin",	VX (4, 522),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vrfin",	VX (4, 522),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"evextsh",	VX (4, 523),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evrndw",	VX (4, 524),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vspltb",	VX (4, 524),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
+{"vspltb",	VX (4, 524),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
 {"evcntlzw",	VX (4, 525),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evcntlsw",	VX (4, 526),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vupkhsb",	VX (4, 526),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vupkhsb",	VX (4, 526),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"brinc",	VX (4, 527),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"ps_abs",	XRC(4, 264,0),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
-{"ps_abs.",	XRC(4, 264,1),	XRA_MASK,    PPCPS,	PPCNONE,	{FRT, FRB}},
+{"ps_abs",	XRC(4, 264,0),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
+{"ps_abs.",	XRC(4, 264,1),	XRA_MASK,    PPCPS,	PPCEFS,		{FRT, FRB}},
 {"evand",	VX (4, 529),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evandc",	VX (4, 530),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evxor",	VX (4, 534),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2208,34 +2208,34 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evcmplts",	VX (4, 563),	VX_MASK,     PPCSPE,	PPCNONE,	{CRFD, RA, RB}},
 {"evcmpeq",	VX (4, 564),	VX_MASK,     PPCSPE,	PPCNONE,	{CRFD, RA, RB}},
 {"cget",	APU(4, 284,0),	APU_RA_MASK, PPC405,	PPCNONE,	{RT, FSL}},
-{"vadduhs",	VX (4, 576),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vminuh",	VX (4, 578),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vsrh",	VX (4, 580),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtuh",	VXR(4, 582,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmuleuh",	VX (4, 584),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vrfiz",	VX (4, 586),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
-{"vsplth",	VX (4, 588),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
-{"vupkhsh",	VX (4, 590),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vadduhs",	VX (4, 576),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vminuh",	VX (4, 578),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vsrh",	VX (4, 580),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtuh",	VXR(4, 582,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmuleuh",	VX (4, 584),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vrfiz",	VX (4, 586),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
+{"vsplth",	VX (4, 588),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
+{"vupkhsh",	VX (4, 590),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"nget",	APU(4, 300,0),	APU_RA_MASK, PPC405,	PPCNONE,	{RT, FSL}},
 {"evsel",	EVSEL(4,79),	EVSEL_MASK,  PPCSPE,	PPCNONE,	{RS, RA, RB, CRFS}},
 {"ncget",	APU(4, 316,0),	APU_RA_MASK, PPC405,	PPCNONE,	{RT, FSL}},
 {"evfsadd",	VX (4, 640),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vadduws",	VX (4, 640),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vadduws",	VX (4, 640),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evfssub",	VX (4, 641),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vminuw",	VX (4, 642),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vminuw",	VX (4, 642),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evfsabs",	VX (4, 644),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vsrw",	VX (4, 644),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsrw",	VX (4, 644),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evfsnabs",	VX (4, 645),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evfsneg",	VX (4, 646),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vcmpgtuw",	VXR(4, 646,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpgtuw",	VXR(4, 646,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evfsmul",	VX (4, 648),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evfsdiv",	VX (4, 649),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vrfip",	VX (4, 650),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vrfip",	VX (4, 650),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"evfscmpgt",	VX (4, 652),	VX_MASK,     PPCSPE,	PPCNONE,	{CRFD, RA, RB}},
-{"vspltw",	VX (4, 652),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
+{"vspltw",	VX (4, 652),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
 {"evfscmplt",	VX (4, 653),	VX_MASK,     PPCSPE,	PPCNONE,	{CRFD, RA, RB}},
 {"evfscmpeq",	VX (4, 654),	VX_MASK,     PPCSPE,	PPCNONE,	{CRFD, RA, RB}},
-{"vupklsb",	VX (4, 654),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vupklsb",	VX (4, 654),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"evfscfui",	VX (4, 656),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB}},
 {"evfscfsi",	VX (4, 657),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB}},
 {"evfscfuf",	VX (4, 658),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RB}},
@@ -2254,17 +2254,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"efsadd",	VX (4, 704),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA, RB}},
 {"efssub",	VX (4, 705),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA, RB}},
 {"efsabs",	VX (4, 708),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA}},
-{"vsr",		VX (4, 708),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsr",		VX (4, 708),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"efsnabs",	VX (4, 709),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA}},
 {"efsneg",	VX (4, 710),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA}},
-{"vcmpgtfp",	VXR(4, 710,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpgtfp",	VXR(4, 710,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"efsmul",	VX (4, 712),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA, RB}},
 {"efsdiv",	VX (4, 713),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RA, RB}},
-{"vrfim",	VX (4, 714),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vrfim",	VX (4, 714),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"efscmpgt",	VX (4, 716),	VX_MASK,     PPCEFS,	PPCNONE,	{CRFD, RA, RB}},
 {"efscmplt",	VX (4, 717),	VX_MASK,     PPCEFS,	PPCNONE,	{CRFD, RA, RB}},
 {"efscmpeq",	VX (4, 718),	VX_MASK,     PPCEFS,	PPCNONE,	{CRFD, RA, RB}},
-{"vupklsh",	VX (4, 718),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vupklsh",	VX (4, 718),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"efscfd",	VX (4, 719),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RB}},
 {"efscfui",	VX (4, 720),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RB}},
 {"efscfsi",	VX (4, 721),	VX_MASK,     PPCEFS,	PPCNONE,	{RS, RB}},
@@ -2310,24 +2310,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"efdtstlt",	VX (4, 765),	VX_MASK,     PPCEFS,	PPCNONE,	{CRFD, RA, RB}},
 {"efdtsteq",	VX (4, 766),	VX_MASK,     PPCEFS,	PPCNONE,	{CRFD, RA, RB}},
 {"evlddx",	VX (4, 768),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vaddsbs",	VX (4, 768),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vaddsbs",	VX (4, 768),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evldd",	VX (4, 769),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_8, RA}},
 {"evldwx",	VX (4, 770),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vminsb",	VX (4, 770),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vminsb",	VX (4, 770),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evldw",	VX (4, 771),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_8, RA}},
 {"evldhx",	VX (4, 772),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vsrab",	VX (4, 772),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsrab",	VX (4, 772),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evldh",	VX (4, 773),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_8, RA}},
-{"vcmpgtsb",	VXR(4, 774,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpgtsb",	VXR(4, 774,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evlhhesplatx",VX (4, 776),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vmulesb",	VX (4, 776),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vmulesb",	VX (4, 776),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evlhhesplat",	VX (4, 777),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_2, RA}},
-{"vcfux",	VX (4, 778),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
+{"vcfux",	VX (4, 778),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
 {"evlhhousplatx",VX(4, 780),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vspltisb",	VX (4, 780),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
+{"vspltisb",	VX (4, 780),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, SIMM}},
 {"evlhhousplat",VX (4, 781),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_2, RA}},
 {"evlhhossplatx",VX(4, 782),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vpkpx",	VX (4, 782),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vpkpx",	VX (4, 782),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evlhhossplat",VX (4, 783),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_2, RA}},
 {"mullhwu",	XRC(4, 392,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evlwhex",	VX (4, 784),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2357,55 +2357,55 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evstwwe",	VX (4, 825),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
 {"evstwwox",	VX (4, 828),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evstwwo",	VX (4, 829),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, EVUIMM_4, RA}},
-{"vaddshs",	VX (4, 832),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vminsh",	VX (4, 834),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vsrah",	VX (4, 836),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtsh",	VXR(4, 838,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vmulesh",	VX (4, 840),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcfsx",	VX (4, 842),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
-{"vspltish",	VX (4, 844),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
-{"vupkhpx",	VX (4, 846),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vaddshs",	VX (4, 832),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vminsh",	VX (4, 834),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vsrah",	VX (4, 836),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtsh",	VXR(4, 838,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vmulesh",	VX (4, 840),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcfsx",	VX (4, 842),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
+{"vspltish",	VX (4, 844),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, SIMM}},
+{"vupkhpx",	VX (4, 846),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"mullhw",	XRC(4, 424,0),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"mullhw.",	XRC(4, 424,1),	X_MASK,      MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhw",	XO (4, 428,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhw.",	XO (4, 428,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmaclhw",	XO (4, 430,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmaclhw.",	XO (4, 430,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vaddsws",	VX (4, 896),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vminsw",	VX (4, 898),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vsraw",	VX (4, 900),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtsw",	VXR(4, 902,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vctuxs",	VX (4, 906),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
-{"vspltisw",	VX (4, 908),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, SIMM}},
+{"vaddsws",	VX (4, 896),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vminsw",	VX (4, 898),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vsraw",	VX (4, 900),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtsw",	VXR(4, 902,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vctuxs",	VX (4, 906),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
+{"vspltisw",	VX (4, 908),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, SIMM}},
 {"maclhwsu",	XO (4, 460,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhwsu.",	XO (4, 460,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vcmpbfp",	VXR(4, 966,0),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vctsxs",	VX (4, 970),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB, UIMM}},
-{"vupklpx",	VX (4, 974),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VB}},
+{"vcmpbfp",	VXR(4, 966,0),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vctsxs",	VX (4, 970),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB, UIMM}},
+{"vupklpx",	VX (4, 974),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VB}},
 {"maclhws",	XO (4, 492,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhws.",	XO (4, 492,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmaclhws",	XO (4, 494,0,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmaclhws.",	XO (4, 494,0,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vsububm",	VX (4,1024),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vavgub",	VX (4,1026),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsububm",	VX (4,1024),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vavgub",	VX (4,1026),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhessf",	VX (4,1027),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vand",	VX (4,1028),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpequb.",	VXR(4,	 6,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vand",	VX (4,1028),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpequb.",	VXR(4,	 6,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi0fcm.",	APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi0fcm",	APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"evmhossf",	VX (4,1031),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmheumi",	VX (4,1032),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhesmi",	VX (4,1033),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vmaxfp",	VX (4,1034),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vmaxfp",	VX (4,1034),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhesmf",	VX (4,1035),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhoumi",	VX (4,1036),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vslo",	VX (4,1036),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vslo",	VX (4,1036),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhosmi",	VX (4,1037),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmf",	VX (4,1039),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"machhwuo",	XO (4,	12,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"machhwuo.",	XO (4,	12,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_merge00",	XOPS(4,528,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"ps_merge00.",	XOPS(4,528,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
+{"ps_merge00",	XOPS(4,528,0),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"ps_merge00.",	XOPS(4,528,1),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
 {"evmhessfa",	VX (4,1059),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhossfa",	VX (4,1063),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmheumia",	VX (4,1064),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2414,17 +2414,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhoumia",	VX (4,1068),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmia",	VX (4,1069),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhosmfa",	VX (4,1071),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vsubuhm",	VX (4,1088),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vavguh",	VX (4,1090),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vandc",	VX (4,1092),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpequh.",	VXR(4,	70,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubuhm",	VX (4,1088),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vavguh",	VX (4,1090),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vandc",	VX (4,1092),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpequh.",	VXR(4,	70,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi1fcm.",	APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi1fcm",	APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},   
 {"evmwhssf",	VX (4,1095),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlumi",	VX (4,1096),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vminfp",	VX (4,1098),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vminfp",	VX (4,1098),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmwhumi",	VX (4,1100),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vsro",	VX (4,1100),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsro",	VX (4,1100),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmwhsmi",	VX (4,1101),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwhsmf",	VX (4,1103),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwssf",	VX (4,1107),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2435,8 +2435,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwsmf",	VX (4,1115),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"nmachhwo",	XO (4,	46,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmachhwo.",	XO (4,	46,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_merge01",	XOPS(4,560,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"ps_merge01.",	XOPS(4,560,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
+{"ps_merge01",	XOPS(4,560,0),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"ps_merge01.",	XOPS(4,560,1),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
 {"evmwhssfa",	VX (4,1127),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlumia",	VX (4,1128),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwhumia",	VX (4,1132),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2446,24 +2446,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwumia",	VX (4,1144),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmia",	VX (4,1145),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwsmfa",	VX (4,1147),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vsubuwm",	VX (4,1152),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vavguw",	VX (4,1154),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vor",		VX (4,1156),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpequw.",	VXR(4, 134,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubuwm",	VX (4,1152),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vavguw",	VX (4,1154),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vor",		VX (4,1156),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpequw.",	VXR(4, 134,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi2fcm.",	APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi2fcm",	APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},   
 {"machhwsuo",	XO (4,	76,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"machhwsuo.",	XO (4,	76,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_merge10",	XOPS(4,592,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"ps_merge10.",	XOPS(4,592,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
+{"ps_merge10",	XOPS(4,592,0),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"ps_merge10.",	XOPS(4,592,1),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
 {"evaddusiaaw",	VX (4,1216),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evaddssiaaw",	VX (4,1217),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evsubfusiaaw",VX (4,1218),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evsubfssiaaw",VX (4,1219),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
 {"evmra",	VX (4,1220),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA}},
-{"vxor",	VX (4,1220),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vxor",	VX (4,1220),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evdivws",	VX (4,1222),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vcmpeqfp.",	VXR(4, 198,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpeqfp.",	VXR(4, 198,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi3fcm.",	APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi3fcm",	APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},   
 {"evdivwu",	VX (4,1223),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2475,14 +2475,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"machhwso.",	XO (4, 108,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmachhwso",	XO (4, 110,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmachhwso.",	XO (4, 110,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"ps_merge11",	XOPS(4,624,0),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
-{"ps_merge11.",	XOPS(4,624,1),	XOPS_MASK,   PPCPS,	PPCNONE,	{FRT, FRA, FRB}},
+{"ps_merge11",	XOPS(4,624,0),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
+{"ps_merge11.",	XOPS(4,624,1),	XOPS_MASK,   PPCPS,	PPCEFS,		{FRT, FRA, FRB}},
 {"evmheusiaaw",	VX (4,1280),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhessiaaw",	VX (4,1281),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vavgsb",	VX (4,1282),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vavgsb",	VX (4,1282),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhessfaaw",	VX (4,1283),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhousiaaw",	VX (4,1284),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vnor",	VX (4,1284),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vnor",	VX (4,1284),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhossiaaw",	VX (4,1285),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"udi4fcm.",	APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi4fcm",	APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
@@ -2503,7 +2503,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhogsmfaa",	VX (4,1327),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlusiaaw",	VX (4,1344),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlssiaaw",	VX (4,1345),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vavgsh",	VX (4,1346),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vavgsh",	VX (4,1346),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi5fcm.",	APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi5fcm",	APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"evmwlumiaaw",	VX (4,1352),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2517,9 +2517,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nmacchwo",	XO (4, 174,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmacchwo.",	XO (4, 174,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"evmheusianw",	VX (4,1408),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vsubcuw",	VX (4,1408),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubcuw",	VX (4,1408),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhessianw",	VX (4,1409),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vavgsw",	VX (4,1410),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vavgsw",	VX (4,1410),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"evmhessfanw",	VX (4,1411),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhousianw",	VX (4,1412),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmhossianw",	VX (4,1413),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2542,7 +2542,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhogsmfan",	VX (4,1455),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlusianw",	VX (4,1472),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"evmwlssianw",	VX (4,1473),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
-{"vcmpgefp.",	VXR(4, 454,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpgefp.",	VXR(4, 454,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi7fcm.",	APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"udi7fcm",	APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,		{URT, URA, URB}},
 {"evmwlumianw",	VX (4,1480),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
@@ -2555,49 +2555,49 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwsmfan",	VX (4,1499),	VX_MASK,     PPCSPE,	PPCNONE,	{RS, RA, RB}},
 {"nmacchwso",	XO (4, 238,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmacchwso.",	XO (4, 238,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vsububs",	VX (4,1536),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mfvscr",	VX (4,1540),	VX_MASK,     PPCVEC,	PPCNONE,	{VD}},
-{"vcmpgtub.",	VXR(4, 518,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsububs",	VX (4,1536),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"mfvscr",	VX (4,1540),	VX_MASK,     PPCVEC,	PPCSPE,		{VD}},
+{"vcmpgtub.",	VXR(4, 518,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi8fcm.",	APU(4, 771,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi8fcm",	APU(4, 771,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"vsum4ubs",	VX (4,1544),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vsubuhs",	VX (4,1600),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"mtvscr",	VX (4,1604),	VX_MASK,     PPCVEC,	PPCNONE,	{VB}},
-{"vcmpgtuh.",	VXR(4, 582,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vsum4shs",	VX (4,1608),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsum4ubs",	VX (4,1544),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vsubuhs",	VX (4,1600),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"mtvscr",	VX (4,1604),	VX_MASK,     PPCVEC,	PPCSPE,		{VB}},
+{"vcmpgtuh.",	VXR(4, 582,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vsum4shs",	VX (4,1608),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi9fcm.",	APU(4, 804,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi9fcm",	APU(4, 804,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"vsubuws",	VX (4,1664),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtuw.",	VXR(4, 646,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubuws",	VX (4,1664),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtuw.",	VXR(4, 646,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi10fcm.",	APU(4, 835,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi10fcm",	APU(4, 835,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"vsum2sws",	VX (4,1672),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtfp.",	VXR(4, 710,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsum2sws",	VX (4,1672),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtfp.",	VXR(4, 710,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi11fcm.",	APU(4, 867,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi11fcm",	APU(4, 867,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"vsubsbs",	VX (4,1792),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtsb.",	VXR(4, 774,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubsbs",	VX (4,1792),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtsb.",	VXR(4, 774,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi12fcm.",	APU(4, 899,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi12fcm",	APU(4, 899,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"vsum4sbs",	VX (4,1800),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsum4sbs",	VX (4,1800),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"maclhwuo",	XO (4, 396,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhwuo.",	XO (4, 396,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vsubshs",	VX (4,1856),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtsh.",	VXR(4, 838,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubshs",	VX (4,1856),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtsh.",	VXR(4, 838,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi13fcm.",	APU(4, 931,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi13fcm",	APU(4, 931,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"maclhwo",	XO (4, 428,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhwo.",	XO (4, 428,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmaclhwo",	XO (4, 430,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"nmaclhwo.",	XO (4, 430,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vsubsws",	VX (4,1920),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
-{"vcmpgtsw.",	VXR(4, 902,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsubsws",	VX (4,1920),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
+{"vcmpgtsw.",	VXR(4, 902,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi14fcm.",	APU(4, 963,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi14fcm",	APU(4, 963,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
-{"vsumsws",	VX (4,1928),	VX_MASK,     PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vsumsws",	VX (4,1928),	VX_MASK,     PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"maclhwsuo",	XO (4, 460,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"maclhwsuo.",	XO (4, 460,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
-{"vcmpbfp.",	VXR(4, 966,1),	VXR_MASK,    PPCVEC,	PPCNONE,	{VD, VA, VB}},
+{"vcmpbfp.",	VXR(4, 966,1),	VXR_MASK,    PPCVEC,	PPCSPE,		{VD, VA, VB}},
 {"udi15fcm.",	APU(4, 995,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"udi15fcm",	APU(4, 995,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
 {"maclhwso",	XO (4, 492,1,0),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
@@ -3458,8 +3458,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"tw",		X(31,4),	 X_MASK,     PPCCOM,	PPCNONE,	{TO, RA, RB}},
 {"t",		X(31,4),	 X_MASK,     PWRCOM,	PPCNONE,	{TO, RA, RB}},
 
-{"lvsl",	X(31,6),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
-{"lvebx",	X(31,7),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
+{"lvsl",	X(31,6),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
+{"lvebx",	X(31,7),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
 {"lbfcmx",	APU(31,7,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"subfc",	XO(31,8,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
@@ -3527,13 +3527,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cmpl",	X(31,32),	XCMP_MASK,   PPC,	PPCNONE,	{BF, L, RA, RB}},
 {"cmpl",	X(31,32),	XCMPL_MASK,  PWRCOM,	PPCNONE,	{BF, RA, RB}},
 
-{"lvsr",	X(31,38),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
-{"lvehx",	X(31,39),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
+{"lvsr",	X(31,38),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
+{"lvehx",	X(31,39),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
 {"lhfcmx",	APU(31,39,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"iselgt",	X(31,47),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},
 
-{"lvewx",	X(31,71),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
+{"lvewx",	X(31,71),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
 
 {"addg6s",	XO(31,74,0,0),	XO_MASK,     POWER6,	PPCNONE,	{RT, RA, RB}},
 
@@ -3608,7 +3608,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lbepx",	X(31,95),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
 
-{"lvx",		X(31,103),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
+{"lvx",		X(31,103),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
 {"lqfcmx",	APU(31,103,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"neg",		XO(31,104,0,0),	XORB_MASK,   COM,	PPCNONE,	{RT, RA}},
@@ -3638,7 +3638,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbtstls",	X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
-{"stvebx",	X(31,135),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
+{"stvebx",	X(31,135),	X_MASK,      PPCVEC,	PPCSPE,		{VS, RA, RB}},
 {"stbfcmx",	APU(31,135,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"subfe",	XO(31,136,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
@@ -3685,7 +3685,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbtls",	X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
-{"stvehx",	X(31,167),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
+{"stvehx",	X(31,167),	X_MASK,      PPCVEC,	PPCSPE,		{VS, RA, RB}},
 {"sthfcmx",	APU(31,167,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"dcbtlse",	X(31,174),	X_MASK,      PPCCHLK,	PPCNONE,	{CT, RA, RB}},
@@ -3706,7 +3706,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"prtyd",	X(31,186),	XRB_MASK, POWER6|PPCA2,	PPCNONE,	{RA, RS}},
 
-{"stvewx",	X(31,199),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
+{"stvewx",	X(31,199),	X_MASK,      PPCVEC,	PPCSPE,		{VS, RA, RB}},
 {"stwfcmx",	APU(31,199,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"subfze",	XO(31,200,0,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
@@ -3741,7 +3741,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icblc",	X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
-{"stvx",	X(31,231),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
+{"stvx",	X(31,231),	X_MASK,      PPCVEC,	PPCSPE,		{VS, RA, RB}},
 {"stqfcmx",	APU(31,231,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"subfme",	XO(31,232,0,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
@@ -3916,7 +3916,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mflctrl2",	XSPR(31,339,157), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfictrl",	XSPR(31,339,158), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfbar",	XSPR(31,339,159), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
-{"mfvrsave",	XSPR(31,339,256), XSPR_MASK, PPCVEC,	PPCNONE,	{RT}},
+{"mfvrsave",	XSPR(31,339,256), XSPR_MASK, PPCVEC,	PPCSPE,		{RT}},
 {"mfusprg0",	XSPR(31,339,256), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
 {"mfsprg",	XSPR(31,339,256), XSPRG_MASK, PPC,	PPCNONE,	{RT, SPRG}},
 {"mfsprg4",	XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RT}},
@@ -4078,11 +4078,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lwax",	X(31,341),	X_MASK,      PPC64,	PPCNONE,	{RT, RA0, RB}},
 
-{"dst",		XDSS(31,342,0),	XDSS_MASK,   PPCVEC,	PPCNONE,	{RA, RB, STRM}},
+{"dst",		XDSS(31,342,0),	XDSS_MASK,   PPCVEC,	PPCSPE,		{RA, RB, STRM}},
 
 {"lhax",	X(31,343),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
 
-{"lvxl",	X(31,359),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
+{"lvxl",	X(31,359),	X_MASK,      PPCVEC,	PPCSPE,		{VD, RA, RB}},
 
 {"abs",		XO(31,360,0,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"abs.",	XO(31,360,0,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
@@ -4098,7 +4098,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lwaux",	X(31,373),	X_MASK,      PPC64,	PPCNONE,	{RT, RAL, RB}},
 
-{"dstst",	XDSS(31,374,0),	XDSS_MASK,   PPCVEC,	PPCNONE,	{RA, RB, STRM}},
+{"dstst",	XDSS(31,374,0),	XDSS_MASK,   PPCVEC,	PPCSPE,		{RA, RB, STRM}},
 
 {"lhaux",	X(31,375),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
 
@@ -4235,7 +4235,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtlctrl2",	XSPR(31,467,157), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtictrl",	XSPR(31,467,158), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtbar",	XSPR(31,467,159), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
-{"mtvrsave",	XSPR(31,467,256), XSPR_MASK, PPCVEC,	PPCNONE,	{RS}},
+{"mtvrsave",	XSPR(31,467,256), XSPR_MASK, PPCVEC,	PPCSPE,		{RS}},
 {"mtusprg0",	XSPR(31,467,256), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
 {"mtsprg",	XSPR(31,467,256), XSPRG_MASK,PPC,	PPCNONE,	{SPRG, RS}},
 {"mtsprg0",	XSPR(31,467,272), XSPR_MASK, PPC,	PPCNONE,	{RS}},
@@ -4370,7 +4370,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
 
-{"stvxl",	X(31,487),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
+{"stvxl",	X(31,487),	X_MASK,      PPCVEC,	PPCSPE,		{VS, RA, RB}},
 
 {"nabs",	XO(31,488,0,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"nabs.",	XO(31,488,0,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
@@ -4417,12 +4417,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ldbrx",	X(31,532),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RT, RA0, RB}},
 
 {"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
-{"lsx",		X(31,533),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
+{"lsx",		X(31,533),	X_MASK,      PWRCOM,	PPCEFS,		{RT, RA, RB}},
 
 {"lwbrx",	X(31,534),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
 {"lbrx",	X(31,534),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"lfsx",	X(31,535),	X_MASK,      COM,	PPCNONE,	{FRT, RA0, RB}},
+{"lfsx",	X(31,535),	X_MASK,      COM,	PPCEFS,		{FRT, RA0, RB}},
 
 {"srw",		XRC(31,536,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
 {"sr",		XRC(31,536,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
@@ -4452,7 +4452,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"tlbsync",	X(31,566),	0xffffffff,  PPC,	PPCNONE,	{0}},
 
-{"lfsux",	X(31,567),	X_MASK,      COM,	PPCNONE,	{FRT, RAS, RB}},
+{"lfsux",	X(31,567),	X_MASK,      COM,	PPCEFS,		{FRT, RAS, RB}},
 
 {"lwdx",	X(31,579),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
 
@@ -4465,16 +4465,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
 
-{"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	PPCNONE,	{0}},
+{"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	PPCSPE,		{0}},
 {"ptesync",	XSYNC(31,598,2), 0xffffffff, PPC64,	PPCNONE,	{0}},
 {"sync",	X(31,598),	XSYNC_MASK,  PPCCOM,	BOOKE|PPC476,	{LS}},
 {"msync",	X(31,598),	0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
 {"dcs",		X(31,598),	0xffffffff,  PWRCOM,	PPCNONE,	{0}},
 
-{"lfdx",	X(31,599),	X_MASK,      COM,	PPCNONE,	{FRT, RA0, RB}},
+{"lfdx",	X(31,599),	X_MASK,      COM,	PPCEFS,		{FRT, RA0, RB}},
 
-{"mffgpr",	XRC(31,607,0),	XRA_MASK,    POWER6,	POWER7,		{FRT, RB}},
-{"lfdepx",	X(31,607),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{FRT, RA, RB}},
+{"mffgpr",	XRC(31,607,0),	XRA_MASK,    POWER6,	POWER7|PPCEFS,	{FRT, RB}},
+{"lfdepx",	X(31,607),	X_MASK,   E500MC|PPCA2,	PPCEFS,	{FRT, RA, RB}},
 
 {"lddx",	X(31,611),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
 
@@ -4490,7 +4490,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dclst",	X(31,630),	XRB_MASK,    PWRCOM,	PPCNONE,	{RS, RA}},
 
-{"lfdux",	X(31,631),	X_MASK,      COM,	PPCNONE,	{FRT, RAS, RB}},
+{"lfdux",	X(31,631),	X_MASK,      COM,	PPCEFS,		{FRT, RAS, RB}},
 
 {"stbdx",	X(31,643),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
 
@@ -4517,7 +4517,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"stwbrx",	X(31,662),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
 {"stbrx",	X(31,662),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
 
-{"stfsx",	X(31,663),	X_MASK,      COM,	PPCNONE,	{FRS, RA0, RB}},
+{"stfsx",	X(31,663),	X_MASK,      COM,	PPCEFS,		{FRS, RA0, RB}},
 
 {"srq",		XRC(31,664,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"srq.",	XRC(31,664,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
@@ -4536,7 +4536,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stbcx.",	XRC(31,694,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},
 
-{"stfsux",	X(31,695),	X_MASK,      COM,	PPCNONE,	{FRS, RAS, RB}},
+{"stfsux",	X(31,695),	X_MASK,      COM,	PPCEFS,		{FRS, RAS, RB}},
 
 {"sriq",	XRC(31,696,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
 {"sriq.",	XRC(31,696,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
@@ -4562,7 +4562,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"sthcx.",	XRC(31,726,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},
 
-{"stfdx",	X(31,727),	X_MASK,      COM,	PPCNONE,	{FRS, RA0, RB}},
+{"stfdx",	X(31,727),	X_MASK,      COM,	PPCEFS,		{FRS, RA0, RB}},
 
 {"srlq",	XRC(31,728,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"srlq.",	XRC(31,728,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
@@ -4570,8 +4570,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sreq",	XRC(31,729,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"sreq.",	XRC(31,729,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 
-{"mftgpr",	XRC(31,735,0),	XRA_MASK,    POWER6,	POWER7,		{RT, FRB}},
-{"stfdepx",	X(31,735),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{FRS, RA, RB}},
+{"mftgpr",	XRC(31,735,0),	XRA_MASK,    POWER6,	POWER7|PPCEFS,	{RT, FRB}},
+{"stfdepx",	X(31,735),	X_MASK,   E500MC|PPCA2,	PPCEFS,		{FRS, RA, RB}},
 
 {"stddx",	X(31,739),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
 
@@ -4598,7 +4598,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dcba",	X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
 {"dcbal",	XOPL(31,758,1), XRT_MASK,    E500MC,	PPCNONE,	{RA, RB}},
 
-{"stfdux",	X(31,759),	X_MASK,      COM,	PPCNONE,	{FRS, RAS, RB}},
+{"stfdux",	X(31,759),	X_MASK,      COM,	PPCEFS,		{FRS, RAS, RB}},
 
 {"srliq",	XRC(31,760,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
 {"srliq.",	XRC(31,760,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
@@ -4622,8 +4622,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lhbrx",	X(31,790),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
 
-{"lfdpx",	X(31,791),	X_MASK,      POWER6,	POWER7,		{FRT, RA, RB}},
-{"lfqx",	X(31,791),	X_MASK,      POWER2,	PPCNONE,	{FRT, RA, RB}},
+{"lfdpx",	X(31,791),	X_MASK,      POWER6,	POWER7|PPCEFS,	{FRT, RA, RB}},
+{"lfqx",	X(31,791),	X_MASK,      POWER2,	PPCEFS,		{FRT, RA, RB}},
 
 {"sraw",	XRC(31,792,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
 {"sra",		XRC(31,792,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
@@ -4633,7 +4633,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"srad",	XRC(31,794,0),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
 {"srad.",	XRC(31,794,1),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
 
-{"lfddx",	X(31,803),	X_MASK,      E500MC,	PPCNONE,	{FRT, RA, RB}},
+{"lfddx",	X(31,803),	X_MASK,      E500MC,	PPCEFS,		{FRT, RA, RB}},
 
 {"lvrxl",	X(31,807),	X_MASK,      CELL,	PPCNONE,	{VD, RA0, RB}},
 
@@ -4643,9 +4643,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lhzcix",	X(31,821),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
 
-{"dss",		XDSS(31,822,0),	XDSS_MASK,   PPCVEC,	PPCNONE,	{STRM}},
+{"dss",		XDSS(31,822,0),	XDSS_MASK,   PPCVEC,	PPCSPE,		{STRM}},
 
-{"lfqux",	X(31,823),	X_MASK,      POWER2,	PPCNONE,	{FRT, RA, RB}},
+{"lfqux",	X(31,823),	X_MASK,      POWER2,	PPCEFS,		{FRT, RA, RB}},
 
 {"srawi",	XRC(31,824,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH}},
 {"srai",	XRC(31,824,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, SH}},
@@ -4670,7 +4670,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mbar",	X(31,854),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{MO}},
 {"eieio",	X(31,854),	0xffffffff, PPCA2|PPC476, PPCNONE,	{0}},
 
-{"lfiwax",	X(31,855),	X_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{FRT, RA0, RB}},
+{"lfiwax",	X(31,855),	X_MASK, POWER6|PPCA2|PPC476, PPCEFS,	{FRT, RA0, RB}},
 
 {"abso",	XO(31,360,1,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"abso.",	XO(31,360,1,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
@@ -4680,7 +4680,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldcix",	X(31,885),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
 
-{"lfiwzx",	X(31,887),	X_MASK,   POWER7|PPCA2,	PPCNONE,	{FRT, RA0, RB}},
+{"lfiwzx",	X(31,887),	X_MASK,   POWER7|PPCA2,	PPCEFS,		{FRT, RA0, RB}},
 
 {"stvlxl",	X(31,903),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
 {"stdfcmux",	APU(31,903,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -4701,8 +4701,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"sthbrx",	X(31,918),	X_MASK,      COM,	PPCNONE,	{RS, RA0, RB}},
 
-{"stfdpx",	X(31,919),	X_MASK,      POWER6,	PPCNONE,	{FRS, RA, RB}},
-{"stfqx",	X(31,919),	X_MASK,      POWER2,	PPCNONE,	{FRS, RA, RB}},
+{"stfdpx",	X(31,919),	X_MASK,      POWER6,	PPCEFS,		{FRS, RA, RB}},
+{"stfqx",	X(31,919),	X_MASK,      POWER2,	PPCEFS,		{FRS, RA, RB}},
 
 {"sraq",	XRC(31,920,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"sraq.",	XRC(31,920,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
@@ -4715,7 +4715,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"extsh.",	XRC(31,922,1),	XRB_MASK,    PPCCOM,	PPCNONE,	{RA, RS}},
 {"exts.",	XRC(31,922,1),	XRB_MASK,    PWRCOM,	PPCNONE,	{RA, RS}},
 
-{"stfddx",	X(31,931),	X_MASK,      E500MC,	PPCNONE,	{FRS, RA, RB}},
+{"stfddx",	X(31,931),	X_MASK,      E500MC,	PPCEFS,		{FRS, RA, RB}},
 
 {"stvrxl",	X(31,935),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
 
@@ -4730,7 +4730,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"sthcix",	X(31,949),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
-{"stfqux",	X(31,951),	X_MASK,      POWER2,	PPCNONE,	{FRS, RA, RB}},
+{"stfqux",	X(31,951),	X_MASK,      POWER2,	PPCEFS,		{FRS, RA, RB}},
 
 {"sraiq",	XRC(31,952,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
 {"sraiq.",	XRC(31,952,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
@@ -4758,7 +4758,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icbi",	X(31,982),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
 
-{"stfiwx",	X(31,983),	X_MASK,      PPC,	PPCNONE,	{FRS, RA0, RB}},
+{"stfiwx",	X(31,983),	X_MASK,      PPC,	PPCEFS,		{FRS, RA0, RB}},
 
 {"extsw",	XRC(31,986,0),  XRB_MASK,    PPC64,	PPCNONE,	{RA, RS}},
 {"extsw.",	XRC(31,986,1),	XRB_MASK,    PPC64,	PPCNONE,	{RA, RS}},
@@ -4791,9 +4791,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cctpm",	0x7c421378,	0xffffffff,  CELL,	PPCNONE,	{0}},
 {"cctph",	0x7c631b78,	0xffffffff,  CELL,	PPCNONE,	{0}},
 
-{"dstt",	XDSS(31,342,1),	XDSS_MASK,   PPCVEC,	PPCNONE,	{RA, RB, STRM}},
-{"dststt",	XDSS(31,374,1),	XDSS_MASK,   PPCVEC,	PPCNONE,	{RA, RB, STRM}},
-{"dssall",	XDSS(31,822,1),	XDSS_MASK,   PPCVEC,	PPCNONE,	{0}},
+{"dstt",	XDSS(31,342,1),	XDSS_MASK,   PPCVEC,	PPCSPE,		{RA, RB, STRM}},
+{"dststt",	XDSS(31,374,1),	XDSS_MASK,   PPCVEC,	PPCSPE,		{RA, RB, STRM}},
+{"dssall",	XDSS(31,822,1),	XDSS_MASK,   PPCVEC,	PPCSPE,		{0}},
 
 {"db8cyc",	0x7f9ce378,	0xffffffff,  CELL,	PPCNONE,	{0}},
 {"db10cyc",	0x7fbdeb78,	0xffffffff,  CELL,	PPCNONE,	{0}},
@@ -4838,143 +4838,143 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"stmw",	OP(47),		OP_MASK,     PPCCOM,	PPCNONE,	{RS, D, RA0}},
 {"stm",		OP(47),		OP_MASK,     PWRCOM,	PPCNONE,	{RS, D, RA0}},
 
-{"lfs",		OP(48),		OP_MASK,     COM,	PPCNONE,	{FRT, D, RA0}},
+{"lfs",		OP(48),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RA0}},
 
-{"lfsu",	OP(49),		OP_MASK,     COM,	PPCNONE,	{FRT, D, RAS}},
+{"lfsu",	OP(49),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RAS}},
 
-{"lfd",		OP(50),		OP_MASK,     COM,	PPCNONE,	{FRT, D, RA0}},
+{"lfd",		OP(50),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RA0}},
 
-{"lfdu",	OP(51),		OP_MASK,     COM,	PPCNONE,	{FRT, D, RAS}},
+{"lfdu",	OP(51),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RAS}},
 
-{"stfs",	OP(52),		OP_MASK,     COM,	PPCNONE,	{FRS, D, RA0}},
+{"stfs",	OP(52),		OP_MASK,     COM,	PPCEFS,		{FRS, D, RA0}},
 
-{"stfsu",	OP(53),		OP_MASK,     COM,	PPCNONE,	{FRS, D, RAS}},
+{"stfsu",	OP(53),		OP_MASK,     COM,	PPCEFS,		{FRS, D, RAS}},
 
 {"stfd",	OP(54),		OP_MASK,     COM,	PPCNONE,	{FRS, D, RA0}},
 
 {"stfdu",	OP(55),		OP_MASK,     COM,	PPCNONE,	{FRS, D, RAS}},
 
 {"lq",		OP(56),		OP_MASK,     POWER4,	PPC476,		{RTQ, DQ, RAQ}},
-{"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
-{"lfq",		OP(56),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
+{"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCEFS,		{FRT,PSD,RA,PSW,PSQ}},
+{"lfq",		OP(56),		OP_MASK,     POWER2,	PPCEFS,		{FRT, D, RA0}},
 
-{"lfdp",	OP(57),		OP_MASK,     POWER6,	POWER7,		{FRT, D, RA0}},
-{"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
-{"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
+{"lfdp",	OP(57),		OP_MASK,     POWER6,	POWER7|PPCEFS,	{FRT, D, RA0}},
+{"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCEFS,		{FRT,PSD,RA,PSW,PSQ}},
+{"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCEFS,		{FRT, D, RA0}},
 
 {"ld",		DSO(58,0),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
 {"ldu",		DSO(58,1),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RAL}},
 {"lwa",		DSO(58,2),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
 
-{"dadd",	XRC(59,2,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"dadd.",	XRC(59,2,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"dadd",	XRC(59,2,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"dadd.",	XRC(59,2,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
 {"dqua",	ZRC(59,3,0),	Z2_MASK,     POWER6,	PPCNONE,	{FRT,FRA,FRB,RMC}},
 {"dqua.",	ZRC(59,3,1),	Z2_MASK,     POWER6,	PPCNONE,	{FRT,FRA,FRB,RMC}},
 
-{"fdivs",	A(59,18,0),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
-{"fdivs.",	A(59,18,1),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
+{"fdivs",	A(59,18,0),	AFRC_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRB}},
+{"fdivs.",	A(59,18,1),	AFRC_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fsubs",	A(59,20,0),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
-{"fsubs.",	A(59,20,1),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
+{"fsubs",	A(59,20,0),	AFRC_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRB}},
+{"fsubs.",	A(59,20,1),	AFRC_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fadds",	A(59,21,0),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
-{"fadds.",	A(59,21,1),	AFRC_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRB}},
+{"fadds",	A(59,21,0),	AFRC_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRB}},
+{"fadds.",	A(59,21,1),	AFRC_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
-{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	TITAN,  	{FRT, FRB}},
+{"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	TITAN|PPCEFS,	{FRT, FRB}},
+{"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	TITAN|PPCEFS,	{FRT, FRB}},
 
-{"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
-{"fres.",	A(59,24,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"fres.",	A(59,24,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
+{"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
+{"fres.",	A(59,24,1),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"fres.",	A(59,24,1),   AFRALFRC_MASK, PPC,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
 
-{"fmuls",	A(59,25,0),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
-{"fmuls.",	A(59,25,1),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
+{"fmuls",	A(59,25,0),	AFRB_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRC}},
+{"fmuls.",	A(59,25,1),	AFRB_MASK,   PPC,	PPCEFS,		{FRT, FRA, FRC}},
 
-{"frsqrtes",	A(59,26,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"frsqrtes",	A(59,26,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
-{"frsqrtes.",	A(59,26,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"frsqrtes.",	A(59,26,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
+{"frsqrtes",	A(59,26,0),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"frsqrtes",	A(59,26,0),   AFRALFRC_MASK, POWER5,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
+{"frsqrtes.",	A(59,26,1),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"frsqrtes.",	A(59,26,1),   AFRALFRC_MASK, POWER5,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
 
-{"fmsubs",	A(59,28,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fmsubs.",	A(59,28,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fmsubs",	A(59,28,0),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fmsubs.",	A(59,28,1),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fmadds",	A(59,29,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fmadds.",	A(59,29,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fmadds",	A(59,29,0),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fmadds.",	A(59,29,1),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fnmsubs",	A(59,30,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnmsubs.",	A(59,30,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fnmsubs",	A(59,30,0),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnmsubs.",	A(59,30,1),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fnmadds",	A(59,31,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnmadds.",	A(59,31,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fnmadds",	A(59,31,0),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnmadds.",	A(59,31,1),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"dmul",	XRC(59,34,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"dmul.",	XRC(59,34,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"dmul",	XRC(59,34,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"dmul.",	XRC(59,34,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"drrnd",	ZRC(59,35,0),	Z2_MASK,     POWER6,	PPCNONE,	{FRT, FRA, FRB, RMC}},
-{"drrnd.",	ZRC(59,35,1),	Z2_MASK,     POWER6,	PPCNONE,	{FRT, FRA, FRB, RMC}},
+{"drrnd",	ZRC(59,35,0),	Z2_MASK,     POWER6,	PPCEFS,		{FRT, FRA, FRB, RMC}},
+{"drrnd.",	ZRC(59,35,1),	Z2_MASK,     POWER6,	PPCEFS,		{FRT, FRA, FRB, RMC}},
 
-{"dscli",	ZRC(59,66,0),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
-{"dscli.",	ZRC(59,66,1),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
+{"dscli",	ZRC(59,66,0),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
+{"dscli.",	ZRC(59,66,1),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
 
-{"dquai",	ZRC(59,67,0),	Z2_MASK,     POWER6,	PPCNONE,	{TE, FRT,FRB,RMC}},
+{"dquai",	ZRC(59,67,0),	Z2_MASK,     POWER6,	PPCEFS,		{TE, FRT,FRB,RMC}},
 {"dquai.",	ZRC(59,67,1),	Z2_MASK,     POWER6,	PPCNONE,	{TE, FRT,FRB,RMC}},
 
-{"dscri",	ZRC(59,98,0),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
-{"dscri.",	ZRC(59,98,1),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
+{"dscri",	ZRC(59,98,0),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
+{"dscri.",	ZRC(59,98,1),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
 
-{"drintx",	ZRC(59,99,0),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
-{"drintx.",	ZRC(59,99,1),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
+{"drintx",	ZRC(59,99,0),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
+{"drintx.",	ZRC(59,99,1),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
 
-{"dcmpo",	X(59,130),	X_MASK,      POWER6,	PPCNONE,	{BF,  FRA, FRB}},
+{"dcmpo",	X(59,130),	X_MASK,      POWER6,	PPCEFS,		{BF,  FRA, FRB}},
 
-{"dtstex",	X(59,162),	X_MASK,      POWER6,	PPCNONE,	{BF,  FRA, FRB}},
-{"dtstdc",	Z(59,194),	Z_MASK,      POWER6,	PPCNONE,	{BF,  FRA, DCM}},
-{"dtstdg",	Z(59,226),	Z_MASK,      POWER6,	PPCNONE,	{BF,  FRA, DGM}},
+{"dtstex",	X(59,162),	X_MASK,      POWER6,	PPCEFS,		{BF,  FRA, FRB}},
+{"dtstdc",	Z(59,194),	Z_MASK,      POWER6,	PPCEFS,		{BF,  FRA, DCM}},
+{"dtstdg",	Z(59,226),	Z_MASK,      POWER6,	PPCEFS,		{BF,  FRA, DGM}},
 
-{"drintn",	ZRC(59,227,0),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
-{"drintn.",	ZRC(59,227,1),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
+{"drintn",	ZRC(59,227,0),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
+{"drintn.",	ZRC(59,227,1),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
 
-{"dctdp",	XRC(59,258,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dctdp.",	XRC(59,258,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dctdp",	XRC(59,258,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dctdp.",	XRC(59,258,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"dctfix",	XRC(59,290,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dctfix.",	XRC(59,290,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dctfix",	XRC(59,290,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dctfix.",	XRC(59,290,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"ddedpd",	XRC(59,322,0),	X_MASK,      POWER6,	PPCNONE,	{SP, FRT, FRB}}, 
-{"ddedpd.",	XRC(59,322,1),	X_MASK,      POWER6,	PPCNONE,	{SP, FRT, FRB}}, 
+{"ddedpd",	XRC(59,322,0),	X_MASK,      POWER6,	PPCEFS,		{SP, FRT, FRB}}, 
+{"ddedpd.",	XRC(59,322,1),	X_MASK,      POWER6,	PPCEFS,		{SP, FRT, FRB}}, 
 
-{"dxex",	XRC(59,354,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dxex.",	XRC(59,354,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dxex",	XRC(59,354,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dxex.",	XRC(59,354,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"dsub",	XRC(59,514,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"dsub.",	XRC(59,514,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"dsub",	XRC(59,514,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"dsub.",	XRC(59,514,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"ddiv",	XRC(59,546,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"ddiv.",	XRC(59,546,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"ddiv",	XRC(59,546,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"ddiv.",	XRC(59,546,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"dcmpu",	X(59,642),	X_MASK,      POWER6,	PPCNONE,	{BF,  FRA, FRB}},
+{"dcmpu",	X(59,642),	X_MASK,      POWER6,	PPCEFS,		{BF,  FRA, FRB}},
 
-{"dtstsf",	X(59,674),	X_MASK,      POWER6,	PPCNONE,	{BF,  FRA, FRB}},
+{"dtstsf",	X(59,674),	X_MASK,      POWER6,	PPCEFS,		{BF,  FRA, FRB}},
 
-{"drsp",	XRC(59,770,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"drsp.",	XRC(59,770,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"drsp",	XRC(59,770,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"drsp.",	XRC(59,770,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"dcffix",	XRC(59,802,0), X_MASK|FRA_MASK, POWER7,	PPCNONE,	{FRT, FRB}},
-{"dcffix.",	XRC(59,802,1), X_MASK|FRA_MASK, POWER7,	PPCNONE,	{FRT, FRB}},
+{"dcffix",	XRC(59,802,0), X_MASK|FRA_MASK, POWER7,	PPCEFS,		{FRT, FRB}},
+{"dcffix.",	XRC(59,802,1), X_MASK|FRA_MASK, POWER7,	PPCEFS,		{FRT, FRB}},
 
-{"denbcd",	XRC(59,834,0),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
-{"denbcd.",	XRC(59,834,1),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
+{"denbcd",	XRC(59,834,0),	X_MASK,      POWER6,	PPCEFS,		{S, FRT, FRB}},
+{"denbcd.",	XRC(59,834,1),	X_MASK,      POWER6,	PPCEFS,		{S, FRT, FRB}},
 
-{"fcfids",	XRC(59,846,0),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
-{"fcfids.",	XRC(59,846,1),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
+{"fcfids",	XRC(59,846,0),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
+{"fcfids.",	XRC(59,846,1),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
 
-{"diex",	XRC(59,866,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"diex.",	XRC(59,866,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"diex",	XRC(59,866,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"diex.",	XRC(59,866,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fcfidus",	XRC(59,974,0),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
-{"fcfidus.",	XRC(59,974,1),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
+{"fcfidus",	XRC(59,974,0),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
+{"fcfidus.",	XRC(59,974,1),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
 
 {"xxsldwi",	XX3(60,2),	XX3SHW_MASK, PPCVSX,	PPCNONE,	{XT6, XA6, XB6, SHW}},
 {"xxsel",	XX4(60,3),	XX4_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6, XC6}},
@@ -5118,234 +5118,234 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xvcvsxddp",	XX2(60,504),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
 {"xvnegdp",	XX2(60,505),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
 
-{"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
-{"stfq",	OP(60),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
+{"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCEFS,		{FRS,PSD,RA,PSW,PSQ}},
+{"stfq",	OP(60),		OP_MASK,     POWER2,	PPCEFS,		{FRS, D, RA}},
 
-{"stfdp",	OP(61),		OP_MASK,     POWER6,	PPCNONE,	{FRT, D, RA0}},
-{"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
-{"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
+{"stfdp",	OP(61),		OP_MASK,     POWER6,	PPCEFS,		{FRT, D, RA0}},
+{"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCEFS,		{FRS,PSD,RA,PSW,PSQ}},
+{"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCEFS,		{FRS, D, RA}},
 
 {"std",		DSO(62,0),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RA0}},
 {"stdu",	DSO(62,1),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RAS}},
 {"stq",		DSO(62,2),	DS_MASK,     POWER4,	PPC476,		{RSQ, DS, RA0}},
 
-{"fcmpu",	X(63,0),     X_MASK|(3<<21), COM,	PPCNONE,	{BF, FRA, FRB}},
+{"fcmpu",	X(63,0),     X_MASK|(3<<21), COM,	PPCEFS,		{BF, FRA, FRB}},
 
-{"daddq",	XRC(63,2,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"daddq.",	XRC(63,2,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"daddq",	XRC(63,2,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"daddq.",	XRC(63,2,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"dquaq",	ZRC(63,3,0),	Z2_MASK,     POWER6,	PPCNONE,	{FRT, FRA, FRB, RMC}},
-{"dquaq.",	ZRC(63,3,1),	Z2_MASK,     POWER6,	PPCNONE,	{FRT, FRA, FRB, RMC}},
+{"dquaq",	ZRC(63,3,0),	Z2_MASK,     POWER6,	PPCEFS,		{FRT, FRA, FRB, RMC}},
+{"dquaq.",	ZRC(63,3,1),	Z2_MASK,     POWER6,	PPCEFS,		{FRT, FRA, FRB, RMC}},
 
 {"fcpsgn",	XRC(63,8,0),	X_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{FRT, FRA, FRB}},
 {"fcpsgn.",	XRC(63,8,1),	X_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{FRT, FRA, FRB}},
 
-{"frsp",	XRC(63,12,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
-{"frsp.",	XRC(63,12,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
+{"frsp",	XRC(63,12,0),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
+{"frsp.",	XRC(63,12,1),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
 
-{"fctiw",	XRC(63,14,0),	XRA_MASK,    PPCCOM,	PPCNONE,	{FRT, FRB}},
-{"fcir",	XRC(63,14,0),	XRA_MASK,    POWER2,	PPCNONE,	{FRT, FRB}},
-{"fctiw.",	XRC(63,14,1),	XRA_MASK,    PPCCOM,	PPCNONE,	{FRT, FRB}},
-{"fcir.",	XRC(63,14,1),	XRA_MASK,    POWER2,	PPCNONE,	{FRT, FRB}},
+{"fctiw",	XRC(63,14,0),	XRA_MASK,    PPCCOM,	PPCEFS,		{FRT, FRB}},
+{"fcir",	XRC(63,14,0),	XRA_MASK,    POWER2,	PPCEFS,		{FRT, FRB}},
+{"fctiw.",	XRC(63,14,1),	XRA_MASK,    PPCCOM,	PPCEFS,		{FRT, FRB}},
+{"fcir.",	XRC(63,14,1),	XRA_MASK,    POWER2,	PPCEFS,		{FRT, FRB}},
 
-{"fctiwz",	XRC(63,15,0),	XRA_MASK,    PPCCOM,	PPCNONE,	{FRT, FRB}},
-{"fcirz",	XRC(63,15,0),	XRA_MASK,    POWER2,	PPCNONE,	{FRT, FRB}},
-{"fctiwz.",	XRC(63,15,1),	XRA_MASK,    PPCCOM,	PPCNONE,	{FRT, FRB}},
-{"fcirz.",	XRC(63,15,1),	XRA_MASK,    POWER2,	PPCNONE,	{FRT, FRB}},
+{"fctiwz",	XRC(63,15,0),	XRA_MASK,    PPCCOM,	PPCEFS,		{FRT, FRB}},
+{"fcirz",	XRC(63,15,0),	XRA_MASK,    POWER2,	PPCEFS,		{FRT, FRB}},
+{"fctiwz.",	XRC(63,15,1),	XRA_MASK,    PPCCOM,	PPCEFS,		{FRT, FRB}},
+{"fcirz.",	XRC(63,15,1),	XRA_MASK,    POWER2,	PPCEFS,		{FRT, FRB}},
 
-{"fdiv",	A(63,18,0),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fd",		A(63,18,0),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fdiv.",	A(63,18,1),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fd.",		A(63,18,1),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
+{"fdiv",	A(63,18,0),	AFRC_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fd",		A(63,18,0),	AFRC_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fdiv.",	A(63,18,1),	AFRC_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fd.",		A(63,18,1),	AFRC_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fsub",	A(63,20,0),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fs",		A(63,20,0),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fsub.",	A(63,20,1),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fs.",		A(63,20,1),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
+{"fsub",	A(63,20,0),	AFRC_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fs",		A(63,20,0),	AFRC_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fsub.",	A(63,20,1),	AFRC_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fs.",		A(63,20,1),	AFRC_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fadd",	A(63,21,0),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fa",		A(63,21,0),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fadd.",	A(63,21,1),	AFRC_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRB}},
-{"fa.",		A(63,21,1),	AFRC_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRB}},
+{"fadd",	A(63,21,0),	AFRC_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fa",		A(63,21,0),	AFRC_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fadd.",	A(63,21,1),	AFRC_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRB}},
+{"fa.",		A(63,21,1),	AFRC_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
-{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	TITAN,  	{FRT, FRB}},
+{"fsqrt",	A(63,22,0),    AFRAFRC_MASK, PPCPWR2,	PPCEFS,		{FRT, FRB}},
+{"fsqrt.",	A(63,22,1),    AFRAFRC_MASK, PPCPWR2,	PPCEFS,		{FRT, FRB}},
 
-{"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fre",		A(63,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"fre",		A(63,24,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
-{"fre.",	A(63,24,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"fre.",	A(63,24,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
+{"fre",		A(63,24,0),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"fre",		A(63,24,0),   AFRALFRC_MASK, POWER5,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
+{"fre.",	A(63,24,1),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"fre.",	A(63,24,1),   AFRALFRC_MASK, POWER5,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
 
-{"fmul",	A(63,25,0),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
-{"fm",		A(63,25,0),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
-{"fmul.",	A(63,25,1),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
-{"fm.",		A(63,25,1),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
+{"fmul",	A(63,25,0),	AFRB_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRC}},
+{"fm",		A(63,25,0),	AFRB_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRC}},
+{"fmul.",	A(63,25,1),	AFRB_MASK,   PPCCOM,	PPCEFS,		{FRT, FRA, FRC}},
+{"fm.",		A(63,25,1),	AFRB_MASK,   PWRCOM,	PPCEFS,		{FRT, FRA, FRC}},
 
-{"frsqrte",	A(63,26,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"frsqrte",	A(63,26,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
-{"frsqrte.",	A(63,26,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
-{"frsqrte.",	A(63,26,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
+{"frsqrte",	A(63,26,0),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"frsqrte",	A(63,26,0),   AFRALFRC_MASK, PPC,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
+{"frsqrte.",	A(63,26,1),   AFRAFRC_MASK,  POWER7,	PPCEFS,		{FRT, FRB}},
+{"frsqrte.",	A(63,26,1),   AFRALFRC_MASK, PPC,	POWER7|PPCEFS,	{FRT, FRB, A_L}},
 
-{"fmsub",	A(63,28,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fms",		A(63,28,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fmsub.",	A(63,28,1),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fms.",	A(63,28,1),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fmsub",	A(63,28,0),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fms",		A(63,28,0),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fmsub.",	A(63,28,1),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fms.",	A(63,28,1),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fmadd",	A(63,29,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fma",		A(63,29,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fmadd.",	A(63,29,1),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fma.",	A(63,29,1),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fmadd",	A(63,29,0),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fma",		A(63,29,0),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fmadd.",	A(63,29,1),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fma.",	A(63,29,1),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fnmsub",	A(63,30,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnms",	A(63,30,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnmsub.",	A(63,30,1),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnms.",	A(63,30,1),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fnmsub",	A(63,30,0),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnms",	A(63,30,0),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnmsub.",	A(63,30,1),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnms.",	A(63,30,1),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fnmadd",	A(63,31,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnma",	A(63,31,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnmadd.",	A(63,31,1),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
-{"fnma.",	A(63,31,1),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
+{"fnmadd",	A(63,31,0),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnma",	A(63,31,0),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnmadd.",	A(63,31,1),	A_MASK,      PPCCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
+{"fnma.",	A(63,31,1),	A_MASK,      PWRCOM,	PPCEFS,		{FRT, FRA, FRC, FRB}},
 
-{"fcmpo",	X(63,32),    X_MASK|(3<<21), COM,	PPCNONE,	{BF, FRA, FRB}},
+{"fcmpo",	X(63,32),    X_MASK|(3<<21), COM,	PPCEFS,		{BF, FRA, FRB}},
 
-{"dmulq",	XRC(63,34,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"dmulq.",	XRC(63,34,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"dmulq",	XRC(63,34,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"dmulq.",	XRC(63,34,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"drrndq",	ZRC(63,35,0),	Z2_MASK,     POWER6,	PPCNONE,	{FRT, FRA, FRB, RMC}},
-{"drrndq.",	ZRC(63,35,1),	Z2_MASK,     POWER6,	PPCNONE,	{FRT, FRA, FRB, RMC}},
+{"drrndq",	ZRC(63,35,0),	Z2_MASK,     POWER6,	PPCEFS,		{FRT, FRA, FRB, RMC}},
+{"drrndq.",	ZRC(63,35,1),	Z2_MASK,     POWER6,	PPCEFS,		{FRT, FRA, FRB, RMC}},
 
-{"mtfsb1",	XRC(63,38,0),	XRARB_MASK,  COM,	PPCNONE,	{BT}},
-{"mtfsb1.",	XRC(63,38,1),	XRARB_MASK,  COM,	PPCNONE,	{BT}},
+{"mtfsb1",	XRC(63,38,0),	XRARB_MASK,  COM,	PPCEFS,		{BT}},
+{"mtfsb1.",	XRC(63,38,1),	XRARB_MASK,  COM,	PPCEFS,		{BT}},
 
-{"fneg",	XRC(63,40,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
-{"fneg.",	XRC(63,40,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
+{"fneg",	XRC(63,40,0),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
+{"fneg.",	XRC(63,40,1),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
 
-{"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM,	PPCNONE,	{BF, BFA}},
+{"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM,	PPCEFS,	{BF, BFA}},
 
-{"dscliq",	ZRC(63,66,0),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
-{"dscliq.",	ZRC(63,66,1),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
+{"dscliq",	ZRC(63,66,0),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
+{"dscliq.",	ZRC(63,66,1),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
 
-{"dquaiq",	ZRC(63,67,0),	Z2_MASK,     POWER6,	PPCNONE,	{TE, FRT, FRB, RMC}},
-{"dquaiq.",	ZRC(63,67,1),	Z2_MASK,     POWER6,	PPCNONE,	{TE, FRT, FRB, RMC}},
+{"dquaiq",	ZRC(63,67,0),	Z2_MASK,     POWER6,	PPCEFS,		{TE, FRT, FRB, RMC}},
+{"dquaiq.",	ZRC(63,67,1),	Z2_MASK,     POWER6,	PPCEFS,		{TE, FRT, FRB, RMC}},
 
-{"mtfsb0",	XRC(63,70,0),	XRARB_MASK,  COM,	PPCNONE,	{BT}},
-{"mtfsb0.",	XRC(63,70,1),	XRARB_MASK,  COM,	PPCNONE,	{BT}},
+{"mtfsb0",	XRC(63,70,0),	XRARB_MASK,  COM,	PPCEFS,		{BT}},
+{"mtfsb0.",	XRC(63,70,1),	XRARB_MASK,  COM,	PPCEFS,		{BT}},
 
-{"fmr",		XRC(63,72,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
-{"fmr.",	XRC(63,72,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
+{"fmr",		XRC(63,72,0),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
+{"fmr.",	XRC(63,72,1),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
 
-{"dscriq",	ZRC(63,98,0),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
-{"dscriq.",	ZRC(63,98,1),	Z_MASK,      POWER6,	PPCNONE,	{FRT, FRA, SH16}},
+{"dscriq",	ZRC(63,98,0),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
+{"dscriq.",	ZRC(63,98,1),	Z_MASK,      POWER6,	PPCEFS,		{FRT, FRA, SH16}},
 
-{"drintxq",	ZRC(63,99,0),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
-{"drintxq.",	ZRC(63,99,1),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
+{"drintxq",	ZRC(63,99,0),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
+{"drintxq.",	ZRC(63,99,1),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
 
-{"ftdiv",	X(63,128),   X_MASK|(3<<21), POWER7,	PPCNONE,	{BF, FRA, FRB}},
+{"ftdiv",	X(63,128),   X_MASK|(3<<21), POWER7,	PPCEFS,		{BF, FRA, FRB}},
 
-{"dcmpoq",	X(63,130),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
+{"dcmpoq",	X(63,130),	X_MASK,      POWER6,	PPCEFS,		{BF, FRA, FRB}},
 
 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
 
-{"fnabs",	XRC(63,136,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
-{"fnabs.",	XRC(63,136,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
+{"fnabs",	XRC(63,136,0),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
+{"fnabs.",	XRC(63,136,1),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
 
-{"fctiwu",	XRC(63,142,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
-{"fctiwu.",	XRC(63,142,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
-{"fctiwuz",	XRC(63,143,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
-{"fctiwuz.",	XRC(63,143,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+{"fctiwu",	XRC(63,142,0),	XRA_MASK,    POWER7,	PPCEFS,		{FRT, FRB}},
+{"fctiwu.",	XRC(63,142,1),	XRA_MASK,    POWER7,	PPCEFS,		{FRT, FRB}},
+{"fctiwuz",	XRC(63,143,0),	XRA_MASK,    POWER7,	PPCEFS,		{FRT, FRB}},
+{"fctiwuz.",	XRC(63,143,1),	XRA_MASK,    POWER7,	PPCEFS,		{FRT, FRB}},
 
-{"ftsqrt",	X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,	{BF, FRB}},
+{"ftsqrt",	X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCEFS,	{BF, FRB}},
 
-{"dtstexq",	X(63,162),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
-{"dtstdcq",	Z(63,194),	Z_MASK,      POWER6,	PPCNONE,	{BF, FRA, DCM}},
-{"dtstdgq",	Z(63,226),	Z_MASK,      POWER6,	PPCNONE,	{BF, FRA, DGM}},
+{"dtstexq",	X(63,162),	X_MASK,      POWER6,	PPCEFS,		{BF, FRA, FRB}},
+{"dtstdcq",	Z(63,194),	Z_MASK,      POWER6,	PPCEFS,		{BF, FRA, DCM}},
+{"dtstdgq",	Z(63,226),	Z_MASK,      POWER6,	PPCEFS,		{BF, FRA, DGM}},
 
-{"drintnq",	ZRC(63,227,0),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
-{"drintnq.",	ZRC(63,227,1),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
+{"drintnq",	ZRC(63,227,0),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
+{"drintnq.",	ZRC(63,227,1),	Z2_MASK,     POWER6,	PPCEFS,		{R, FRT, FRB, RMC}},
 
-{"dctqpq",	XRC(63,258,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dctqpq.",	XRC(63,258,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dctqpq",	XRC(63,258,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dctqpq.",	XRC(63,258,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"fabs",	XRC(63,264,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
-{"fabs.",	XRC(63,264,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
+{"fabs",	XRC(63,264,0),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
+{"fabs.",	XRC(63,264,1),	XRA_MASK,    COM,	PPCEFS,		{FRT, FRB}},
 
-{"dctfixq",	XRC(63,290,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dctfixq.",	XRC(63,290,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dctfixq",	XRC(63,290,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dctfixq.",	XRC(63,290,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"ddedpdq",	XRC(63,322,0),	X_MASK,      POWER6,	PPCNONE,	{SP, FRT, FRB}},
-{"ddedpdq.",	XRC(63,322,1),	X_MASK,      POWER6,	PPCNONE,	{SP, FRT, FRB}},
+{"ddedpdq",	XRC(63,322,0),	X_MASK,      POWER6,	PPCEFS,		{SP, FRT, FRB}},
+{"ddedpdq.",	XRC(63,322,1),	X_MASK,      POWER6,	PPCEFS,		{SP, FRT, FRB}},
 
-{"dxexq",	XRC(63,354,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dxexq.",	XRC(63,354,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dxexq",	XRC(63,354,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dxexq.",	XRC(63,354,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"frin",	XRC(63,392,0),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"frin.",	XRC(63,392,1),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"friz",	XRC(63,424,0),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"friz.",	XRC(63,424,1),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"frip",	XRC(63,456,0),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"frip.",	XRC(63,456,1),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"frim",	XRC(63,488,0),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
-{"frim.",	XRC(63,488,1),	XRA_MASK,    POWER5,	PPCNONE,	{FRT, FRB}},
+{"frin",	XRC(63,392,0),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"frin.",	XRC(63,392,1),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"friz",	XRC(63,424,0),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"friz.",	XRC(63,424,1),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"frip",	XRC(63,456,0),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"frip.",	XRC(63,456,1),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"frim",	XRC(63,488,0),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
+{"frim.",	XRC(63,488,1),	XRA_MASK,    POWER5,	PPCEFS,		{FRT, FRB}},
 
-{"dsubq",	XRC(63,514,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"dsubq.",	XRC(63,514,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"dsubq",	XRC(63,514,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"dsubq.",	XRC(63,514,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"ddivq",	XRC(63,546,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"ddivq.",	XRC(63,546,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"ddivq",	XRC(63,546,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"ddivq.",	XRC(63,546,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"mffs",	XRC(63,583,0),	XRARB_MASK,  COM,	PPCNONE,	{FRT}},
-{"mffs.",	XRC(63,583,1),	XRARB_MASK,  COM,	PPCNONE,	{FRT}},
+{"mffs",	XRC(63,583,0),	XRARB_MASK,  COM,	PPCEFS,		{FRT}},
+{"mffs.",	XRC(63,583,1),	XRARB_MASK,  COM,	PPCEFS,		{FRT}},
 
-{"dcmpuq",	X(63,642),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
+{"dcmpuq",	X(63,642),	X_MASK,      POWER6,	PPCEFS,		{BF, FRA, FRB}},
 
-{"dtstsfq",	X(63,674),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
+{"dtstsfq",	X(63,674),	X_MASK,      POWER6,	PPCEFS,		{BF, FRA, FRB}},
 
 {"mtfsf",	XFL(63,711,0),	XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{FLM, FRB, XFL_L, W}},
 {"mtfsf",	XFL(63,711,0),	XFL_MASK,    COM, POWER6|PPCA2|PPC476,	{FLM, FRB}},
 {"mtfsf.",	XFL(63,711,1),	XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{FLM, FRB, XFL_L, W}},
 {"mtfsf.",	XFL(63,711,1),	XFL_MASK,    COM, POWER6|PPCA2|PPC476,	{FLM, FRB}},
 
-{"drdpq",	XRC(63,770,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"drdpq.",	XRC(63,770,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"drdpq",	XRC(63,770,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"drdpq.",	XRC(63,770,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"dcffixq",	XRC(63,802,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
-{"dcffixq.",	XRC(63,802,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
+{"dcffixq",	XRC(63,802,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
+{"dcffixq.",	XRC(63,802,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRB}},
 
-{"fctid",	XRC(63,814,0),	XRA_MASK,    PPC64,	PPCNONE,	{FRT, FRB}},
-{"fctid",	XRC(63,814,0),	XRA_MASK,    PPC476,	PPCNONE,	{FRT, FRB}},
-{"fctid.",	XRC(63,814,1),	XRA_MASK,    PPC64,	PPCNONE,	{FRT, FRB}},
-{"fctid.",	XRC(63,814,1),	XRA_MASK,    PPC476,	PPCNONE,	{FRT, FRB}},
+{"fctid",	XRC(63,814,0),	XRA_MASK,    PPC64,	PPCEFS,		{FRT, FRB}},
+{"fctid",	XRC(63,814,0),	XRA_MASK,    PPC476,	PPCEFS,		{FRT, FRB}},
+{"fctid.",	XRC(63,814,1),	XRA_MASK,    PPC64,	PPCEFS,		{FRT, FRB}},
+{"fctid.",	XRC(63,814,1),	XRA_MASK,    PPC476,	PPCEFS,		{FRT, FRB}},
 
-{"fctidz",	XRC(63,815,0),	XRA_MASK,    PPC64,	PPCNONE,	{FRT, FRB}},
-{"fctidz",	XRC(63,815,0),	XRA_MASK,    PPC476,	PPCNONE,	{FRT, FRB}},
-{"fctidz.",	XRC(63,815,1),	XRA_MASK,    PPC64,	PPCNONE,	{FRT, FRB}},
-{"fctidz.",	XRC(63,815,1),	XRA_MASK,    PPC476,	PPCNONE,	{FRT, FRB}},
+{"fctidz",	XRC(63,815,0),	XRA_MASK,    PPC64,	PPCEFS,		{FRT, FRB}},
+{"fctidz",	XRC(63,815,0),	XRA_MASK,    PPC476,	PPCEFS,		{FRT, FRB}},
+{"fctidz.",	XRC(63,815,1),	XRA_MASK,    PPC64,	PPCEFS,		{FRT, FRB}},
+{"fctidz.",	XRC(63,815,1),	XRA_MASK,    PPC476,	PPCEFS,		{FRT, FRB}},
 
-{"denbcdq",	XRC(63,834,0),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
-{"denbcdq.",	XRC(63,834,1),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
+{"denbcdq",	XRC(63,834,0),	X_MASK,      POWER6,	PPCEFS,		{S, FRT, FRB}},
+{"denbcdq.",	XRC(63,834,1),	X_MASK,      POWER6,	PPCEFS,		{S, FRT, FRB}},
 
-{"fcfid",	XRC(63,846,0),	XRA_MASK,    PPC64,	PPCNONE,	{FRT, FRB}},
-{"fcfid",	XRC(63,846,0),	XRA_MASK,    PPC476,	PPCNONE,	{FRT, FRB}},
-{"fcfid.",	XRC(63,846,1),	XRA_MASK,    PPC64,	PPCNONE,	{FRT, FRB}},
-{"fcfid.",	XRC(63,846,1),	XRA_MASK,    PPC476,	PPCNONE,	{FRT, FRB}},
+{"fcfid",	XRC(63,846,0),	XRA_MASK,    PPC64,	PPCEFS,		{FRT, FRB}},
+{"fcfid",	XRC(63,846,0),	XRA_MASK,    PPC476,	PPCEFS,		{FRT, FRB}},
+{"fcfid.",	XRC(63,846,1),	XRA_MASK,    PPC64,	PPCEFS,		{FRT, FRB}},
+{"fcfid.",	XRC(63,846,1),	XRA_MASK,    PPC476,	PPCEFS,		{FRT, FRB}},
 
-{"diexq",	XRC(63,866,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
-{"diexq.",	XRC(63,866,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
+{"diexq",	XRC(63,866,0),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
+{"diexq.",	XRC(63,866,1),	X_MASK,      POWER6,	PPCEFS,		{FRT, FRA, FRB}},
 
-{"fctidu",	XRC(63,942,0),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
-{"fctidu.",	XRC(63,942,1),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
+{"fctidu",	XRC(63,942,0),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
+{"fctidu.",	XRC(63,942,1),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
 
-{"fctiduz",	XRC(63,943,0),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
-{"fctiduz.",	XRC(63,943,1),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
+{"fctiduz",	XRC(63,943,0),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
+{"fctiduz.",	XRC(63,943,1),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
 
-{"fcfidu",	XRC(63,974,0),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
-{"fcfidu.",	XRC(63,974,1),	XRA_MASK, POWER7|PPCA2,	PPCNONE,	{FRT, FRB}},
+{"fcfidu",	XRC(63,974,0),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
+{"fcfidu.",	XRC(63,974,1),	XRA_MASK, POWER7|PPCA2,	PPCEFS,		{FRT, FRB}},
 };
 
 const int powerpc_num_opcodes =
-- 
1.7.0.5



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