GAS manual formatting fixes

Andreas Schwab schwab@redhat.com
Mon Jun 21 10:50:00 GMT 2010


Remove extra whitespace between grouped @table items.  Installed as
obvious.

Andreas.

2010-06-21  Andreas Schwab  <schwab@redhat.com>

	* doc/as.texinfo (Overview): Use @itemx for grouped @table
	items.
	* doc/c-alpha.texi (Alpha Options): Likewise.
	* doc/c-arm.texi (ARM Directives): Likewise.
	* doc/c-bfin.texi (Blackfin Options): Likewise.
	* doc/c-d10v.texi (D10V-Opts): Likewise.
	* doc/c-i386.texi (i386-Options): Likewise.
	* doc/c-ia64.texi (IA-64 Options): Likewise.
	* doc/c-m68k.texi (M68K-Opts): Likewise.
	* doc/c-tic54x.texi (TIC54X-Directives): Likewise.
	* doc/internals.texi (Symbols): Likewise.

Index: doc/as.texinfo
===================================================================
RCS file: /cvs/src/src/gas/doc/as.texinfo,v
retrieving revision 1.219
diff -a -u -p -a -u -p -r1.219 as.texinfo
--- doc/as.texinfo	8 Jun 2010 10:30:55 -0000	1.219
+++ doc/as.texinfo	21 Jun 2010 10:38:44 -0000
@@ -743,7 +743,8 @@ This option specifies the target process
 is not used in assembler.
 @item -mfdpic
 Assemble for the FDPIC ABI.
-@item -mno-fdpic/-mnopic
+@item -mno-fdpic
+@itemx -mnopic
 Disable -mfdpic.
 @end table
 @end ifset
Index: doc/c-alpha.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-alpha.texi,v
retrieving revision 1.10
diff -a -u -p -a -u -p -r1.10 c-alpha.texi
--- doc/c-alpha.texi	2 Sep 2009 07:24:21 -0000	1.10
+++ doc/c-alpha.texi	21 Jun 2010 10:38:44 -0000
@@ -93,7 +93,7 @@ can still be useful in specific applicat
 @cindex @code{-replace} command line option, Alpha
 @cindex @code{-noreplace} command line option, Alpha
 @item -replace
-@item -noreplace
+@itemx -noreplace
 Enables or disables the optimization of procedure calls, both at assemblage
 and at link time.  These options are only available for VMS targets and
 @code{-replace} is the default.  See section 1.4.1 of the OpenVMS Linker
Index: doc/c-arm.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-arm.texi,v
retrieving revision 1.71
diff -a -u -p -a -u -p -r1.71 c-arm.texi
--- doc/c-arm.texi	15 Apr 2010 10:56:37 -0000	1.71
+++ doc/c-arm.texi	21 Jun 2010 10:38:44 -0000
@@ -538,7 +538,7 @@ for the @option{-mcpu} commandline optio
 
 @cindex @code{.dn} and @code{.qn} directives, ARM
 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
-@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
+@itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
 
 The @code{dn} and @code{qn} directives are used to create typed
 and/or indexed register aliases for use in Advanced SIMD Extension
@@ -655,8 +655,8 @@ directive.
 
 @cindex @code{.inst} directive, ARM
 @item .inst @var{opcode} [ , @dots{} ]
-@item .inst.n @var{opcode} [ , @dots{} ]
-@item .inst.w @var{opcode} [ , @dots{} ]
+@itemx .inst.n @var{opcode} [ , @dots{} ]
+@itemx .inst.w @var{opcode} [ , @dots{} ]
 Generates the instruction corresponding to the numerical value @var{opcode}.
 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
 specified explicitly, overriding the normal encoding rules.
Index: doc/c-bfin.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-bfin.texi,v
retrieving revision 1.7
diff -a -u -p -a -u -p -r1.7 c-bfin.texi
--- doc/c-bfin.texi	10 Mar 2010 13:03:29 -0000	1.7
+++ doc/c-bfin.texi	21 Jun 2010 10:38:44 -0000
@@ -74,7 +74,8 @@ Assemble for the FDPIC ABI.
 
 @cindex @code{-mno-fdpic} command line option, Blackfin
 @cindex @code{-mnopic} command line option, Blackfin
-@item -mno-fdpic/-mnopic
+@item -mno-fdpic
+@itemx -mnopic
 Disable -mfdpic.
 @end table
 
Index: doc/c-d10v.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-d10v.texi,v
retrieving revision 1.5
diff -a -u -p -a -u -p -r1.5 c-d10v.texi
--- doc/c-d10v.texi	3 Mar 2005 01:29:53 -0000	1.5
+++ doc/c-d10v.texi	21 Jun 2010 10:38:44 -0000
@@ -36,7 +36,7 @@ To optimize execution performance, @code
 order of instructions. Normally this generates a warning. When this option 
 is used, no warning will be generated when instructions are swapped.
 @item --gstabs-packing
-@item --no-gstabs-packing
+@itemx --no-gstabs-packing
 @code{@value{AS}} packs adjacent short instructions into a single packed
 instruction. @samp{--no-gstabs-packing} turns instruction packing off if
 @samp{--gstabs} is specified as well; @samp{--gstabs-packing} (the
Index: doc/c-i386.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-i386.texi,v
retrieving revision 1.48
diff -a -u -p -a -u -p -r1.48 c-i386.texi
--- doc/c-i386.texi	3 Feb 2010 20:36:13 -0000	1.48
+++ doc/c-i386.texi	21 Jun 2010 10:38:44 -0000
@@ -180,8 +180,8 @@ with VEX prefix.
 @cindex @samp{-msse-check=} option, i386
 @cindex @samp{-msse-check=} option, x86-64
 @item -msse-check=@var{none}
-@item -msse-check=@var{warning}
-@item -msse-check=@var{error}
+@itemx -msse-check=@var{warning}
+@itemx -msse-check=@var{error}
 These options control if the assembler should check SSE intructions.
 @option{-msse-check=@var{none}} will make the assembler not to check SSE
 instructions,  which is the default.  @option{-msse-check=@var{warning}}
@@ -192,7 +192,7 @@ for any SSE intruction.
 @cindex @samp{-mavxscalar=} option, i386
 @cindex @samp{-mavxscalar=} option, x86-64
 @item -mavxscalar=@var{128}
-@item -mavxscalar=@var{256}
+@itemx -mavxscalar=@var{256}
 This options control how the assembler should encode scalar AVX
 instructions.  @option{-mavxscalar=@var{128}} will encode scalar
 AVX instructions with 128bit vector length, which is the default.
@@ -202,7 +202,7 @@ with 256bit vector length.
 @cindex @samp{-mmnemonic=} option, i386
 @cindex @samp{-mmnemonic=} option, x86-64
 @item -mmnemonic=@var{att}
-@item -mmnemonic=@var{intel}
+@itemx -mmnemonic=@var{intel}
 This option specifies instruction mnemonic for matching instructions. 
 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
 take precedent.
@@ -210,7 +210,7 @@ take precedent.
 @cindex @samp{-msyntax=} option, i386
 @cindex @samp{-msyntax=} option, x86-64
 @item -msyntax=@var{att}
-@item -msyntax=@var{intel}
+@itemx -msyntax=@var{intel}
 This option specifies instruction syntax when processing instructions. 
 The @code{.att_syntax} and @code{.intel_syntax} directives will
 take precedent.
Index: doc/c-ia64.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-ia64.texi,v
retrieving revision 1.10
diff -a -u -p -a -u -p -r1.10 c-ia64.texi
--- doc/c-ia64.texi	12 Feb 2010 14:34:45 -0000	1.10
+++ doc/c-ia64.texi	21 Jun 2010 10:38:44 -0000
@@ -53,25 +53,25 @@ affect the machine code emitted by the a
 turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
 
 @item -milp32
-@item -milp64
-@item -mlp64
-@item -mp64
+@itemx -milp64
+@itemx -mlp64
+@itemx -mp64
 These options select the data model.  The assembler defaults to @code{-mlp64}
 (LP64 data model).
 
 @item -mle
-@item -mbe
+@itemx -mbe
 These options select the byte order.  The @code{-mle} option selects little-endian
 byte order (default) and @code{-mbe} selects big-endian byte order.  Note that
 IA-64 machine code always uses little-endian byte order.
 
 @item -mtune=itanium1
-@item -mtune=itanium2
+@itemx -mtune=itanium2
 Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The
 default is @var{itanium2}.
 
 @item -munwind-check=warning
-@item -munwind-check=error
+@itemx -munwind-check=error
 These options control what the assembler will do when performing
 consistency checks on unwind directives.  @code{-munwind-check=warning}
 will make the assembler issue a warning when an unwind directive check
@@ -79,8 +79,8 @@ fails.  This is the default.  @code{-mun
 assembler issue an error when an unwind directive check fails.
 
 @item -mhint.b=ok
-@item -mhint.b=warning
-@item -mhint.b=error
+@itemx -mhint.b=warning
+@itemx -mhint.b=error
 These options control what the assembler will do when the @samp{hint.b}
 instruction is used.  @code{-mhint.b=ok} will make the assembler accept
 @samp{hint.b}.  @code{-mint.b=warning} will make the assembler issue a
@@ -88,7 +88,7 @@ warning when @samp{hint.b} is used.  @co
 the assembler treat @samp{hint.b} as an error, which is the default.
 
 @item -x
-@item -xexplicit
+@itemx -xexplicit
 These options turn on dependency violation checking.
 
 @item -xauto
Index: doc/c-m68k.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-m68k.texi,v
retrieving revision 1.11
diff -a -u -p -a -u -p -r1.11 c-m68k.texi
--- doc/c-m68k.texi	2 Sep 2009 07:24:21 -0000	1.11
+++ doc/c-m68k.texi	21 Jun 2010 10:38:44 -0000
@@ -65,12 +65,12 @@ for instruction generation, rather than 
 @cindex @samp{-m[no-]mac} command line option, M680x0
 @cindex @samp{-m[no-]emac} command line option, M680x0
 @item -m[no-]68851
-@item -m[no-]68881
-@item -m[no-]div
-@item -m[no-]usp
-@item -m[no-]float
-@item -m[no-]mac
-@item -m[no-]emac
+@itemx -m[no-]68881
+@itemx -m[no-]div
+@itemx -m[no-]usp
+@itemx -m[no-]float
+@itemx -m[no-]mac
+@itemx -m[no-]emac
 
 Enable or disable various architecture specific features.  If a chip
 or architecture by default supports an option (for instance
@@ -210,19 +210,19 @@ Assemble for the 68060.
 Assemble for the CPU32 family of chips.
 
 @item -m5200
-@item -m5202
-@item -m5204
-@item -m5206
-@item -m5206e
-@item -m521x
-@item -m5249
-@item -m528x
-@item -m5307
-@item -m5407
-@item -m547x
-@item -m548x
-@item -mcfv4
-@item -mcfv4e
+@itemx -m5202
+@itemx -m5204
+@itemx -m5206
+@itemx -m5206e
+@itemx -m521x
+@itemx -m5249
+@itemx -m528x
+@itemx -m5307
+@itemx -m5407
+@itemx -m547x
+@itemx -m548x
+@itemx -mcfv4
+@itemx -mcfv4e
 Assemble for the ColdFire family of chips.
 
 @item -m68881
Index: doc/c-tic54x.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-tic54x.texi,v
retrieving revision 1.7
diff -a -u -p -a -u -p -r1.7 c-tic54x.texi
--- doc/c-tic54x.texi	2 Sep 2009 07:24:21 -0000	1.7
+++ doc/c-tic54x.texi	21 Jun 2010 10:38:44 -0000
@@ -531,7 +531,7 @@ only macro definitions.   The standard i
 @cindex @code{mlist} directive, TIC54X
 @cindex @code{mnolist} directive, TIC54X
 @item .mlist
-@item .mnolist
+@itemx .mnolist
 Control whether to include macro and loop block expansions in the
 listing output.  Ignored.
 
Index: doc/internals.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/internals.texi,v
retrieving revision 1.64
diff -a -u -p -a -u -p -r1.64 internals.texi
--- doc/internals.texi	2 Sep 2009 07:24:21 -0000	1.64
+++ doc/internals.texi	21 Jun 2010 10:38:44 -0000
@@ -252,8 +252,8 @@ Indicate that the symbol is a forward re
 be determined upon use.
 
 @item S_GET_TYPE
-@item S_GET_DESC
-@item S_GET_OTHER
+@itemx S_GET_DESC
+@itemx S_GET_OTHER
 @cindex S_GET_TYPE
 @cindex S_GET_DESC
 @cindex S_GET_OTHER
@@ -262,8 +262,8 @@ are only defined for object file formats
 a.out).
 
 @item S_SET_TYPE
-@item S_SET_DESC
-@item S_SET_OTHER
+@itemx S_SET_DESC
+@itemx S_SET_OTHER
 @cindex S_SET_TYPE
 @cindex S_SET_DESC
 @cindex S_SET_OTHER

-- 
Andreas Schwab, schwab@redhat.com
GPG Key fingerprint = D4E8 DBE3 3813 BB5D FA84  5EC7 45C6 250E 6F00 984E
"And now for something completely different."



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