[PATCH] AMD bdver2 processors 2/2 - TBM
Quentin Neill
quentin.neill.gnu@gmail.com
Mon Dec 20 22:40:00 GMT 2010
These two patches add support for BMI and TBM ISAs to be introduced in
AMD bdver2 processors.
The full encoding specification is delayed, however I have posted
abbreviated specs on the gcc mailing list:
BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
Tested on x86-64 with "make -k check RUNTESTFLAGS=i386.exp".
Okay to commit?
--
Quentin
-------------- next part --------------
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 08f908d..e32617e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
2010-12-20 Quentin Neill <quentin.neill@amd.com>
+ * doc/c-i386.texi (i386-TBM): New section.
+
+ * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
+
+
+2010-12-20 Quentin Neill <quentin.neill@amd.com>
+
* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
(build_modrm_byte): Add BMI instruction encoding.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 4c12e9f..a21fcb1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -717,6 +717,8 @@ static const arch_entry cpu_arch[] =
CPU_ABM_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
CPU_BMI_FLAGS, 0, 0 },
+ { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
+ CPU_TBM_FLAGS, 0, 0 },
};
#ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index fd315b0..5da3e27 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,6 +35,7 @@ extending the Intel architecture to 64-bits.
* i386-Float:: Floating Point
* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
* i386-LWP:: AMD's Lightweight Profiling Instructions
+* i386-TBM:: AMD's Trailing Bit Manipulation Instructions
* i386-BMI:: Bit Manipulation Instructions
* i386-16bit:: Writing 16-bit Code
* i386-Arch:: Specifying an x86 CPU architecture
@@ -843,6 +844,22 @@ For detailed information on the LWP instruction set, see the
@cite{AMD Lightweight Profiling Specification} available at
@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
+@node i386-TBM
+@section AMD's Trailing Bit Manipulation Instructions
+
+@cindex TBM, i386
+@cindex TBM, x86-64
+
+@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
+instruction set, available on AMD's BDVER2 processors (Trinity and
+Viperfish).
+
+TBM instructions provide instructions implementing individual bit
+manipulation operations such as isolating, masking, setting, resetting,
+complementing, and operations on trailing zeros and ones.
+
+@c Need to add a specification citation here.
+
@node i386-BMI
@section Bit Manipulation Instructions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 01faa8d..71a6058 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,22 @@
2010-12-20 Quentin Neill <quentin.neill@amd.com>
+ * gas/i386/i386.exp: Run tbm and x86-64-tbm.
+ * gas/i386/tbm.d: New.
+ * gas/i386/tbm.s: New.
+ * gas/i386/x86-64-tbm.d: New.
+ * gas/i386/x86-64-tbm.s: New.
+ * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
+ * gas/i386/arch-10.s: Add a TBM instruction.
+ * gas/i386/arch-10-1.l: Add TBM instruction pattern.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/x86-64-arch-2.s: Likewise.
+ * gas/i386/x86-64-arch-2.d: Likewise.
+
+
+2010-12-20 Quentin Neill <quentin.neill@amd.com>
+
* gas/i386/i386.exp: Run bmi and x86-64-bmi.
* gas/i386/bmi.d: New.
* gas/i386/bmi.s: New.
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 95f4425..706a7a8 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -30,6 +30,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -97,7 +98,9 @@ GAS LISTING .*
[ ]*58[ ]+lzcnt %ecx,%ebx
[ ]*59[ ]+\# PadLock
[ ]*60[ ]+xstorerng
-[ ]*61[ ]+\# BMI
-[ ]*62[ ]+blsr %ecx,%ebx
-[ ]*63[ ]+\# nop
-[ ]*64[ ]+nopl \(%eax\)
+[ ]*61[ ]+\# TBM
+[ ]*62[ ]+blcfill %ecx,%ebx
+[ ]*63[ ]+\# BMI
+[ ]*64[ ]+blsr %ecx,%ebx
+[ ]*65[ ]+\# nop
+[ ]*66[ ]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index 3e9d68f..a6b6542 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -29,6 +29,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -96,7 +97,9 @@ GAS LISTING .*
[ ]*58[ ]+lzcnt %ecx,%ebx
[ ]*59[ ]+\# PadLock
[ ]*60[ ]+xstorerng
-[ ]*61[ ]+\# BMI
-[ ]*62[ ]+blsr %ecx,%ebx
-[ ]*63[ ]+\# nop
-[ ]*64[ ]+nopl \(%eax\)
+[ ]*61[ ]+\# TBM
+[ ]*62[ ]+blcfill %ecx,%ebx
+[ ]*63[ ]+\# BMI
+[ ]*64[ ]+blsr %ecx,%ebx
+[ ]*65[ ]+\# nop
+[ ]*66[ ]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 7183ea0..afc94e2 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -22,6 +22,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -92,7 +93,9 @@ GAS LISTING .*
[ ]*58[ ]+lzcnt %ecx,%ebx
[ ]*59[ ]+\# PadLock
[ ]*60[ ]+xstorerng
-[ ]*61[ ]+\# BMI
-[ ]*62[ ]+blsr %ecx,%ebx
-[ ]*63[ ]+\# nop
-[ ]*64[ ]+nopl \(%eax\)
+[ ]*61[ ]+\# TBM
+[ ]*62[ ]+blcfill %ecx,%ebx
+[ ]*63[ ]+\# BMI
+[ ]*64[ ]+blsr %ecx,%ebx
+[ ]*65[ ]+\# nop
+[ ]*66[ ]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 7cd68a3..ae7702c 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -20,6 +20,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -90,7 +91,9 @@ GAS LISTING .*
[ ]*58[ ]+lzcnt %ecx,%ebx
[ ]*59[ ]+\# PadLock
[ ]*60[ ]+xstorerng
-[ ]*61[ ]+\# BMI
-[ ]*62[ ]+blsr %ecx,%ebx
-[ ]*63[ ]+\# nop
-[ ]*64[ ]+nopl \(%eax\)
+[ ]*61[ ]+\# TBM
+[ ]*62[ ]+blcfill %ecx,%ebx
+[ ]*63[ ]+\# BMI
+[ ]*64[ ]+blsr %ecx,%ebx
+[ ]*65[ ]+\# nop
+[ ]*66[ ]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 6e40abd..ae5d098 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+tbm+bmi
#objdump: -dw
#name: i386 arch 10
@@ -36,6 +36,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 da vmload
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
+[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
#pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index 7c669eb..9a70258 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -58,6 +58,8 @@ vmload
lzcnt %ecx,%ebx
# PadLock
xstorerng
+# TBM
+blcfill %ecx,%ebx
# BMI
blsr %ecx,%ebx
# nop
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 01a3ecb..aee5330 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "fma4"
run_dump_test "lwp"
run_dump_test "xop"
+ run_dump_test "tbm"
run_dump_test "bmi"
run_dump_test "f16c"
run_dump_test "f16c-intel"
@@ -373,6 +374,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-fma4"
run_dump_test "x86-64-lwp"
run_dump_test "x86-64-xop"
+ run_dump_test "x86-64-tbm"
run_dump_test "x86-64-bmi"
run_dump_test "x86-64-f16c"
run_dump_test "x86-64-f16c-intel"
diff --git a/gas/testsuite/gas/i386/tbm.d b/gas/testsuite/gas/i386/tbm.d
new file mode 100644
index 0000000..29a4b08
--- /dev/null
+++ b/gas/testsuite/gas/i386/tbm.d
@@ -0,0 +1,168 @@
+#objdump: -dw
+#name: i386 TBM
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 8f ea 78 10 1c f2 67 00 00 00 bextr \$0x67,\(%edx,%esi,8\),%ebx
+[ ]*[a-f0-9]+: 8f ea 78 10 c6 00 00 00 00 bextr \$0x0,%esi,%eax
+[ ]*[a-f0-9]+: 8f ea 78 10 f8 ff ff ff 7f bextr \$0x7fffffff,%eax,%edi
+[ ]*[a-f0-9]+: 8f ea 78 10 26 b2 35 00 00 bextr \$0x35b2,\(%esi\),%esp
+[ ]*[a-f0-9]+: 8f ea 78 10 ef 86 9c 00 00 bextr \$0x9c86,%edi,%ebp
+[ ]*[a-f0-9]+: 8f ea 78 10 c9 03 00 00 00 bextr \$0x3,%ecx,%ecx
+[ ]*[a-f0-9]+: 8f ea 78 10 74 43 fd ee 00 00 00 bextr \$0xee,-0x3\(%ebx,%eax,2\),%esi
+[ ]*[a-f0-9]+: 8f ea 78 10 23 55 00 00 00 bextr \$0x55,\(%ebx\),%esp
+[ ]*[a-f0-9]+: 8f ea 78 10 12 e8 4e 00 00 bextr \$0x4ee8,\(%edx\),%edx
+[ ]*[a-f0-9]+: 8f ea 78 10 fb 00 00 00 00 bextr \$0x0,%ebx,%edi
+[ ]*[a-f0-9]+: 8f ea 78 10 f4 dc 00 00 00 bextr \$0xdc,%esp,%esi
+[ ]*[a-f0-9]+: 8f ea 78 10 00 a9 00 00 00 bextr \$0xa9,\(%eax\),%eax
+[ ]*[a-f0-9]+: 8f ea 78 10 ea 89 01 00 00 bextr \$0x189,%edx,%ebp
+[ ]*[a-f0-9]+: 8f ea 78 10 0c 41 84 00 00 00 bextr \$0x84,\(%ecx,%eax,2\),%ecx
+[ ]*[a-f0-9]+: 8f ea 78 10 04 01 fe ca 00 00 bextr \$0xcafe,\(%ecx,%eax,1\),%eax
+[ ]*[a-f0-9]+: 8f ea 78 10 bc 3e 09 71 00 00 ad de 00 00 bextr \$0xdead,0x7109\(%esi,%edi,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 09 blcfill \(%ecx\),%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 ce blcfill %esi,%edi
+[ ]*[a-f0-9]+: 8f e9 70 01 c8 blcfill %eax,%ecx
+[ ]*[a-f0-9]+: 8f e9 48 01 cf blcfill %edi,%esi
+[ ]*[a-f0-9]+: 8f e9 58 01 0e blcfill \(%esi\),%esp
+[ ]*[a-f0-9]+: 8f e9 50 01 0b blcfill \(%ebx\),%ebp
+[ ]*[a-f0-9]+: 8f e9 68 01 8c 03 95 1a 00 00 blcfill 0x1a95\(%ebx,%eax,1\),%edx
+[ ]*[a-f0-9]+: 8f e9 40 01 0a blcfill \(%edx\),%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 cb blcfill %ebx,%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 8c 30 ce 00 00 00 blcfill 0xce\(%eax,%esi,1\),%eax
+[ ]*[a-f0-9]+: 8f e9 78 01 0c 1d 02 35 ff ff blcfill -0xcafe\(,%ebx,1\),%eax
+[ ]*[a-f0-9]+: 8f e9 60 01 0c 05 a1 51 ff ff blcfill -0xae5f\(,%eax,1\),%ebx
+[ ]*[a-f0-9]+: 8f e9 40 01 c9 blcfill %ecx,%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 cc blcfill %esp,%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 cd blcfill %ebp,%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 0c 4e blcfill \(%esi,%ecx,2\),%eax
+[ ]*[a-f0-9]+: 8f e9 70 02 f0 blci %eax,%ecx
+[ ]*[a-f0-9]+: 8f e9 60 02 f1 blci %ecx,%ebx
+[ ]*[a-f0-9]+: 8f e9 78 02 34 45 b0 12 00 00 blci 0x12b0\(,%eax,2\),%eax
+[ ]*[a-f0-9]+: 8f e9 40 02 30 blci \(%eax\),%edi
+[ ]*[a-f0-9]+: 8f e9 48 02 f7 blci %edi,%esi
+[ ]*[a-f0-9]+: 8f e9 68 02 f4 blci %esp,%edx
+[ ]*[a-f0-9]+: 8f e9 50 02 f6 blci %esi,%ebp
+[ ]*[a-f0-9]+: 8f e9 78 02 f2 blci %edx,%eax
+[ ]*[a-f0-9]+: 8f e9 58 02 b4 83 57 8d ff ff blci -0x72a9\(%ebx,%eax,4\),%esp
+[ ]*[a-f0-9]+: 8f e9 60 02 36 blci \(%esi\),%ebx
+[ ]*[a-f0-9]+: 8f e9 78 02 34 73 blci \(%ebx,%esi,2\),%eax
+[ ]*[a-f0-9]+: 8f e9 68 02 33 blci \(%ebx\),%edx
+[ ]*[a-f0-9]+: 8f e9 78 02 f3 blci %ebx,%eax
+[ ]*[a-f0-9]+: 8f e9 70 02 b4 93 a2 e0 00 00 blci 0xe0a2\(%ebx,%edx,4\),%ecx
+[ ]*[a-f0-9]+: 8f e9 40 02 37 blci \(%edi\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 02 34 45 ff ff ff 3f blci 0x3fffffff\(,%eax,2\),%eax
+[ ]*[a-f0-9]+: 8f e9 70 01 ef blcic %edi,%ecx
+[ ]*[a-f0-9]+: 8f e9 40 01 e8 blcic %eax,%edi
+[ ]*[a-f0-9]+: 8f e9 60 01 28 blcic \(%eax\),%ebx
+[ ]*[a-f0-9]+: 8f e9 68 01 e9 blcic %ecx,%edx
+[ ]*[a-f0-9]+: 8f e9 58 01 ee blcic %esi,%esp
+[ ]*[a-f0-9]+: 8f e9 50 01 2c 1d 02 35 ff ff blcic -0xcafe\(,%ebx,1\),%ebp
+[ ]*[a-f0-9]+: 8f e9 78 01 ed blcic %ebp,%eax
+[ ]*[a-f0-9]+: 8f e9 48 01 2e blcic \(%esi\),%esi
+[ ]*[a-f0-9]+: 8f e9 60 01 ec blcic %esp,%ebx
+[ ]*[a-f0-9]+: 8f e9 48 01 2c 3f blcic \(%edi,%edi,1\),%esi
+[ ]*[a-f0-9]+: 8f e9 50 01 2c 35 01 00 00 c0 blcic -0x3fffffff\(,%esi,1\),%ebp
+[ ]*[a-f0-9]+: 8f e9 40 01 2b blcic \(%ebx\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 6c c7 08 blcic 0x8\(%edi,%eax,8\),%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 a9 d1 4a 57 3a blcic 0x3a574ad1\(%ecx\),%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 ec blcic %esp,%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 ea blcic %edx,%edi
+[ ]*[a-f0-9]+: 8f e9 40 02 48 0c blcmsk 0xc\(%eax\),%edi
+[ ]*[a-f0-9]+: 8f e9 50 02 0c 16 blcmsk \(%esi,%edx,1\),%ebp
+[ ]*[a-f0-9]+: 8f e9 70 02 8f 00 22 3d e2 blcmsk -0x1dc2de00\(%edi\),%ecx
+[ ]*[a-f0-9]+: 8f e9 58 02 c8 blcmsk %eax,%esp
+[ ]*[a-f0-9]+: 8f e9 78 02 0c 57 blcmsk \(%edi,%edx,2\),%eax
+[ ]*[a-f0-9]+: 8f e9 68 02 0b blcmsk \(%ebx\),%edx
+[ ]*[a-f0-9]+: 8f e9 40 02 0a blcmsk \(%edx\),%edi
+[ ]*[a-f0-9]+: 8f e9 48 02 ce blcmsk %esi,%esi
+[ ]*[a-f0-9]+: 8f e9 40 02 cc blcmsk %esp,%edi
+[ ]*[a-f0-9]+: 8f e9 58 02 cf blcmsk %edi,%esp
+[ ]*[a-f0-9]+: 8f e9 60 02 0c c3 blcmsk \(%ebx,%eax,8\),%ebx
+[ ]*[a-f0-9]+: 8f e9 78 02 0f blcmsk \(%edi\),%eax
+[ ]*[a-f0-9]+: 8f e9 78 02 ca blcmsk %edx,%eax
+[ ]*[a-f0-9]+: 8f e9 40 02 4c 3b 67 blcmsk 0x67\(%ebx,%edi,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 40 02 0c 05 a0 d8 12 aa blcmsk -0x55ed2760\(,%eax,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 02 0c 05 01 00 00 00 blcmsk 0x1\(,%eax,1\),%eax
+[ ]*[a-f0-9]+: 8f e9 48 01 da blcs %edx,%esi
+[ ]*[a-f0-9]+: 8f e9 78 01 1b blcs \(%ebx\),%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 d8 blcs %eax,%edi
+[ ]*[a-f0-9]+: 8f e9 58 01 9c 01 fe ca 00 00 blcs 0xcafe\(%ecx,%eax,1\),%esp
+[ ]*[a-f0-9]+: 8f e9 50 01 df blcs %edi,%ebp
+[ ]*[a-f0-9]+: 8f e9 70 01 1a blcs \(%edx\),%ecx
+[ ]*[a-f0-9]+: 8f e9 40 01 1f blcs \(%edi\),%edi
+[ ]*[a-f0-9]+: 8f e9 60 01 9b 02 35 ff ff blcs -0xcafe\(%ebx\),%ebx
+[ ]*[a-f0-9]+: 8f e9 70 01 dc blcs %esp,%ecx
+[ ]*[a-f0-9]+: 8f e9 68 01 de blcs %esi,%edx
+[ ]*[a-f0-9]+: 8f e9 40 01 18 blcs \(%eax\),%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 1c 0d 01 00 00 00 blcs 0x1\(,%ecx,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 d9 blcs %ecx,%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 1c 13 blcs \(%ebx,%edx,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 9c 00 53 21 ff ff blcs -0xdead\(%eax,%eax,1\),%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 1c 13 blcs \(%ebx,%edx,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 d0 blsfill %eax,%eax
+[ ]*[a-f0-9]+: 8f e9 48 01 d1 blsfill %ecx,%esi
+[ ]*[a-f0-9]+: 8f e9 40 01 10 blsfill \(%eax\),%edi
+[ ]*[a-f0-9]+: 8f e9 58 01 d3 blsfill %ebx,%esp
+[ ]*[a-f0-9]+: 8f e9 68 01 d2 blsfill %edx,%edx
+[ ]*[a-f0-9]+: 8f e9 70 01 11 blsfill \(%ecx\),%ecx
+[ ]*[a-f0-9]+: 8f e9 40 01 d7 blsfill %edi,%edi
+[ ]*[a-f0-9]+: 8f e9 50 01 d5 blsfill %ebp,%ebp
+[ ]*[a-f0-9]+: 8f e9 40 01 17 blsfill \(%edi\),%edi
+[ ]*[a-f0-9]+: 8f e9 60 01 13 blsfill \(%ebx\),%ebx
+[ ]*[a-f0-9]+: 8f e9 78 01 16 blsfill \(%esi\),%eax
+[ ]*[a-f0-9]+: 8f e9 78 01 14 80 blsfill \(%eax,%eax,4\),%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 d6 blsfill %esi,%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 94 18 21 a2 00 00 blsfill 0xa221\(%eax,%ebx,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 14 00 blsfill \(%eax,%eax,1\),%eax
+[ ]*[a-f0-9]+: 8f e9 70 01 14 5d f8 ff ff ff blsfill -0x8\(,%ebx,2\),%ecx
+[ ]*[a-f0-9]+: 8f e9 40 01 f0 blsic %eax,%edi
+[ ]*[a-f0-9]+: 8f e9 60 01 36 blsic \(%esi\),%ebx
+[ ]*[a-f0-9]+: 8f e9 50 01 34 5d 00 00 00 00 blsic 0x0\(,%ebx,2\),%ebp
+[ ]*[a-f0-9]+: 8f e9 78 01 34 41 blsic \(%ecx,%eax,2\),%eax
+[ ]*[a-f0-9]+: 8f e9 58 01 37 blsic \(%edi\),%esp
+[ ]*[a-f0-9]+: 8f e9 78 01 33 blsic \(%ebx\),%eax
+[ ]*[a-f0-9]+: 8f e9 70 01 f7 blsic %edi,%ecx
+[ ]*[a-f0-9]+: 8f e9 40 01 74 18 51 blsic 0x51\(%eax,%ebx,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 68 01 f4 blsic %esp,%edx
+[ ]*[a-f0-9]+: 8f e9 68 01 74 3e 99 blsic -0x67\(%esi,%edi,1\),%edx
+[ ]*[a-f0-9]+: 8f e9 40 01 31 blsic \(%ecx\),%edi
+[ ]*[a-f0-9]+: 8f e9 48 01 74 8e 67 blsic 0x67\(%esi,%ecx,4\),%esi
+[ ]*[a-f0-9]+: 8f e9 40 01 b4 d3 81 00 00 00 blsic 0x81\(%ebx,%edx,8\),%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 74 11 0e blsic 0xe\(%ecx,%edx,1\),%edi
+[ ]*[a-f0-9]+: 8f e9 58 01 70 3b blsic 0x3b\(%eax\),%esp
+[ ]*[a-f0-9]+: 8f e9 40 01 f1 blsic %ecx,%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 f8 t1mskc %eax,%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 ff t1mskc %edi,%edi
+[ ]*[a-f0-9]+: 8f e9 70 01 39 t1mskc \(%ecx\),%ecx
+[ ]*[a-f0-9]+: 8f e9 48 01 3c 33 t1mskc \(%ebx,%esi,1\),%esi
+[ ]*[a-f0-9]+: 8f e9 50 01 fa t1mskc %edx,%ebp
+[ ]*[a-f0-9]+: 8f e9 68 01 3c 0d 00 00 00 00 t1mskc 0x0\(,%ecx,1\),%edx
+[ ]*[a-f0-9]+: 8f e9 58 01 3c b5 00 00 00 00 t1mskc 0x0\(,%esi,4\),%esp
+[ ]*[a-f0-9]+: 8f e9 70 01 fb t1mskc %ebx,%ecx
+[ ]*[a-f0-9]+: 8f e9 60 01 3b t1mskc \(%ebx\),%ebx
+[ ]*[a-f0-9]+: 8f e9 40 01 fc t1mskc %esp,%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 38 t1mskc \(%eax\),%edi
+[ ]*[a-f0-9]+: 8f e9 78 01 f9 t1mskc %ecx,%eax
+[ ]*[a-f0-9]+: 8f e9 40 01 b8 ad de 00 00 t1mskc 0xdead\(%eax\),%edi
+[ ]*[a-f0-9]+: 8f e9 68 01 f9 t1mskc %ecx,%edx
+[ ]*[a-f0-9]+: 8f e9 60 01 3c 15 ad de 00 00 t1mskc 0xdead\(,%edx,1\),%ebx
+[ ]*[a-f0-9]+: 8f e9 40 01 3a t1mskc \(%edx\),%edi
+[ ]*[a-f0-9]+: 8f e9 58 01 23 tzmsk \(%ebx\),%esp
+[ ]*[a-f0-9]+: 8f e9 78 01 e7 tzmsk %edi,%eax
+[ ]*[a-f0-9]+: 8f e9 48 01 a7 02 35 ff ff tzmsk -0xcafe\(%edi\),%esi
+[ ]*[a-f0-9]+: 8f e9 68 01 24 3d 00 00 00 00 tzmsk 0x0\(,%edi,1\),%edx
+[ ]*[a-f0-9]+: 8f e9 50 01 e0 tzmsk %eax,%ebp
+[ ]*[a-f0-9]+: 8f e9 60 01 e5 tzmsk %ebp,%ebx
+[ ]*[a-f0-9]+: 8f e9 40 01 26 tzmsk \(%esi\),%edi
+[ ]*[a-f0-9]+: 8f e9 70 01 21 tzmsk \(%ecx\),%ecx
+[ ]*[a-f0-9]+: 8f e9 40 01 24 45 00 00 00 00 tzmsk 0x0\(,%eax,2\),%edi
+[ ]*[a-f0-9]+: 8f e9 40 01 e7 tzmsk %edi,%edi
+[ ]*[a-f0-9]+: 8f e9 68 01 e4 tzmsk %esp,%edx
+[ ]*[a-f0-9]+: 8f e9 70 01 20 tzmsk \(%eax\),%ecx
+[ ]*[a-f0-9]+: 8f e9 78 01 24 3a tzmsk \(%edx,%edi,1\),%eax
+[ ]*[a-f0-9]+: 8f e9 78 01 23 tzmsk \(%ebx\),%eax
+[ ]*[a-f0-9]+: 8f e9 78 01 a3 d9 c6 2a 2a tzmsk 0x2a2ac6d9\(%ebx\),%eax
+[ ]*[a-f0-9]+: 8f e9 70 01 a4 01 47 e9 ff ff tzmsk -0x16b9\(%ecx,%eax,1\),%ecx
diff --git a/gas/testsuite/gas/i386/tbm.s b/gas/testsuite/gas/i386/tbm.s
new file mode 100644
index 0000000..1f970ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/tbm.s
@@ -0,0 +1,167 @@
+
+ .allow_index_reg
+ .text
+
+_start:
+
+ BEXTR $0x67,(%edx,%esi,8),%ebx
+ BEXTR $0x0,%esi,%eax
+ BEXTR $0x7FFFFFFF,%eax,%edi
+ BEXTR $0x35B2,(%esi),%esp
+ BEXTR $0x9C86,%edi,%ebp
+ BEXTR $0x3,%ecx,%ecx
+ BEXTR $0xEE,-0x3(%ebx,%eax,2),%esi
+ BEXTR $0x55,(%ebx),%esp
+ BEXTR $0x4EE8,(%edx),%edx
+ BEXTR $0x0,%ebx,%edi
+ BEXTR $0xDC,%esp,%esi
+ BEXTR $0xA9,(%eax),%eax
+ BEXTR $0x189,%edx,%ebp
+ BEXTR $0x84,0x0(%ecx,%eax,2),%ecx
+ BEXTR $0xCAFE,(%ecx,%eax),%eax
+ BEXTR $0xDEAD,0x7109(%esi,%edi),%edi
+ BLCFILL (%ecx),%eax
+ BLCFILL %esi,%edi
+ BLCFILL %eax,%ecx
+ BLCFILL %edi,%esi
+ BLCFILL (%esi),%esp
+ BLCFILL (%ebx),%ebp
+ BLCFILL 0x1A95(%ebx,%eax),%edx
+ BLCFILL (%edx),%edi
+ BLCFILL %ebx,%edi
+ BLCFILL 0xCE(%eax,%esi),%eax
+ BLCFILL -0xCAFE(,%ebx,1),%eax
+ BLCFILL -0xAE5F(,%eax),%ebx
+ BLCFILL %ecx,%edi
+ BLCFILL %esp,%eax
+ BLCFILL %ebp,%edi
+ BLCFILL (%esi,%ecx,2),%eax
+ BLCI %eax,%ecx
+ BLCI %ecx,%ebx
+ BLCI 0x12B0(,%eax,2),%eax
+ BLCI (%eax),%edi
+ BLCI %edi,%esi
+ BLCI %esp,%edx
+ BLCI %esi,%ebp
+ BLCI %edx,%eax
+ BLCI -0x72A9(%ebx,%eax,4),%esp
+ BLCI (%esi),%ebx
+ BLCI (%ebx,%esi,2),%eax
+ BLCI (%ebx),%edx
+ BLCI %ebx,%eax
+ BLCI 0xE0A2(%ebx,%edx,4),%ecx
+ BLCI (%edi),%edi
+ BLCI 0x3FFFFFFF(,%eax,2),%eax
+ BLCIC %edi,%ecx
+ BLCIC %eax,%edi
+ BLCIC (%eax),%ebx
+ BLCIC %ecx,%edx
+ BLCIC %esi,%esp
+ BLCIC -0xCAFE(,%ebx),%ebp
+ BLCIC %ebp,%eax
+ BLCIC (%esi),%esi
+ BLCIC %esp,%ebx
+ BLCIC 0x0(%edi,%edi,1),%esi
+ BLCIC -0x3FFFFFFF(,%esi),%ebp
+ BLCIC (%ebx),%edi
+ BLCIC 0x8(%edi,%eax,8),%eax
+ BLCIC 0x3A574AD1(%ecx),%edi
+ BLCIC %esp,%edi
+ BLCIC %edx,%edi
+ BLCMSK 0xC(%eax),%edi
+ BLCMSK (%esi,%edx),%ebp
+ BLCMSK -0x1DC2DE00(%edi),%ecx
+ BLCMSK %eax,%esp
+ BLCMSK 0x0(%edi,%edx,2),%eax
+ BLCMSK (%ebx),%edx
+ BLCMSK (%edx),%edi
+ BLCMSK %esi,%esi
+ BLCMSK %esp,%edi
+ BLCMSK %edi,%esp
+ BLCMSK -0x0(%ebx,%eax,8),%ebx
+ BLCMSK (%edi),%eax
+ BLCMSK %edx,%eax
+ BLCMSK 0x67(%ebx,%edi),%edi
+ BLCMSK -0x55ED2760(,%eax),%edi
+ BLCMSK 0x1(,%eax),%eax
+ BLCS %edx,%esi
+ BLCS (%ebx),%eax
+ BLCS %eax,%edi
+ BLCS 0xCAFE(%ecx,%eax),%esp
+ BLCS %edi,%ebp
+ BLCS (%edx),%ecx
+ BLCS (%edi),%edi
+ BLCS -0xCAFE(%ebx),%ebx
+ BLCS %esp,%ecx
+ BLCS %esi,%edx
+ BLCS (%eax),%edi
+ BLCS 0x1(,%ecx,1),%edi
+ BLCS %ecx,%eax
+ BLCS (%ebx,%edx),%edi
+ BLCS -0xDEAD(%eax,%eax),%eax
+ BLCS 0x0(%ebx,%edx),%edi
+ BLSFILL %eax,%eax
+ BLSFILL %ecx,%esi
+ BLSFILL (%eax),%edi
+ BLSFILL %ebx,%esp
+ BLSFILL %edx,%edx
+ BLSFILL (%ecx),%ecx
+ BLSFILL %edi,%edi
+ BLSFILL %ebp,%ebp
+ BLSFILL (%edi),%edi
+ BLSFILL (%ebx),%ebx
+ BLSFILL (%esi),%eax
+ BLSFILL (%eax,%eax,4),%eax
+ BLSFILL %esi,%edi
+ BLSFILL 0xA221(%eax,%ebx),%edi
+ BLSFILL (%eax,%eax,1),%eax
+ BLSFILL -0x8(,%ebx,2),%ecx
+ BLSIC %eax,%edi
+ BLSIC (%esi),%ebx
+ BLSIC (,%ebx,2),%ebp
+ BLSIC (%ecx,%eax,2),%eax
+ BLSIC (%edi),%esp
+ BLSIC (%ebx),%eax
+ BLSIC %edi,%ecx
+ BLSIC 0x51(%eax,%ebx,1),%edi
+ BLSIC %esp,%edx
+ BLSIC -0x67(%esi,%edi),%edx
+ BLSIC (%ecx),%edi
+ BLSIC 0x67(%esi,%ecx,4),%esi
+ BLSIC 0x81(%ebx,%edx,8),%edi
+ BLSIC 0xE(%ecx,%edx),%edi
+ BLSIC 0x3B(%eax),%esp
+ BLSIC %ecx,%edi
+ T1MSKC %eax,%eax
+ T1MSKC %edi,%edi
+ T1MSKC (%ecx),%ecx
+ T1MSKC (%ebx,%esi,1),%esi
+ T1MSKC %edx,%ebp
+ T1MSKC 0x0(,%ecx,1),%edx
+ T1MSKC (,%esi,4),%esp
+ T1MSKC %ebx,%ecx
+ T1MSKC (%ebx),%ebx
+ T1MSKC %esp,%edi
+ T1MSKC (%eax),%edi
+ T1MSKC %ecx,%eax
+ T1MSKC 0xDEAD(%eax),%edi
+ T1MSKC %ecx,%edx
+ T1MSKC 0xDEAD(,%edx),%ebx
+ T1MSKC (%edx),%edi
+ TZMSK (%ebx),%esp
+ TZMSK %edi,%eax
+ TZMSK -0xCAFE(%edi),%esi
+ TZMSK (,%edi,1),%edx
+ TZMSK %eax,%ebp
+ TZMSK %ebp,%ebx
+ TZMSK (%esi),%edi
+ TZMSK (%ecx),%ecx
+ TZMSK (,%eax,2),%edi
+ TZMSK %edi,%edi
+ TZMSK %esp,%edx
+ TZMSK (%eax),%ecx
+ TZMSK (%edx,%edi),%eax
+ TZMSK (%ebx),%eax
+ TZMSK 0x2A2AC6D9(%ebx),%eax
+ TZMSK -0x16B9(%ecx,%eax,1),%ecx
+
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index ac09453..36c335a 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+tbm+bmi
#objdump: -dw
#name: x86-64 arch 2
@@ -36,5 +36,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 da vmload
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
+[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index 962f15e..5d574ee 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,5 +58,7 @@ vmload
lzcnt %ecx,%ebx
# PadLock
xstorerng
+# TBM
+blcfill %ecx,%ebx
# BMI
blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-tbm.d b/gas/testsuite/gas/i386/x86-64-tbm.d
new file mode 100644
index 0000000..b6807bb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-tbm.d
@@ -0,0 +1,328 @@
+#objdump: -dw
+#name: x86-64 TBM
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 8f 6a 78 10 f8 00 00 00 00 bextr \$0x0,%eax,%r15d
+[ ]*[a-f0-9]+: 8f 4a 78 10 d7 f1 4d 00 00 bextr \$0x4df1,%r15d,%r10d
+[ ]*[a-f0-9]+: 8f 4a 78 10 f5 92 5e a5 2d bextr \$0x2da55e92,%r13d,%r14d
+[ ]*[a-f0-9]+: 67 8f 8a 78 10 44 7d 06 ff ff ff 7f bextr \$0x7fffffff,0x6\(%r13d,%r15d,2\),%eax
+[ ]*[a-f0-9]+: 8f ca 78 10 eb 61 f7 1e 25 bextr \$0x251ef761,%r11d,%ebp
+[ ]*[a-f0-9]+: 8f 6a 78 10 3c d7 39 2b 00 00 bextr \$0x2b39,\(%rdi,%rdx,8\),%r15d
+[ ]*[a-f0-9]+: 8f 2a 78 10 0c 35 ad de 00 00 92 00 00 00 bextr \$0x92,0xdead\(,%r14,1\),%r9d
+[ ]*[a-f0-9]+: 8f ca 78 10 75 00 87 68 00 00 bextr \$0x6887,0x0\(%r13\),%esi
+[ ]*[a-f0-9]+: 67 8f ca 78 10 09 0d 00 00 00 bextr \$0xd,\(%r9d\),%ecx
+[ ]*[a-f0-9]+: 8f ea 78 10 1c 05 d8 40 00 00 2b 00 00 00 bextr \$0x2b,0x40d8\(,%rax,1\),%ebx
+[ ]*[a-f0-9]+: 8f 4a 78 10 00 2d ea 00 00 bextr \$0xea2d,\(%r8\),%r8d
+[ ]*[a-f0-9]+: 67 8f 4a 78 10 65 00 6c 00 00 00 bextr \$0x6c,0x0\(%r13d\),%r12d
+[ ]*[a-f0-9]+: 8f 6a 78 10 1c 0d 8f 8c 00 00 3b 9e 00 00 bextr \$0x9e3b,0x8c8f\(,%rcx,1\),%r11d
+[ ]*[a-f0-9]+: 67 8f ca 78 10 24 02 0f 00 00 00 bextr \$0xf,\(%r10d,%eax,1\),%esp
+[ ]*[a-f0-9]+: 67 8f aa 78 10 3c cd 00 00 00 00 ad de 00 00 bextr \$0xdead,0x0\(,%r9d,8\),%edi
+[ ]*[a-f0-9]+: 8f ca 78 10 c0 fe ca 00 00 bextr \$0xcafe,%r8d,%eax
+[ ]*[a-f0-9]+: 8f 4a f8 10 81 bc 10 00 00 b9 3b 26 7d bextr \$0x7d263bb9,0x10bc\(%r9\),%r8
+[ ]*[a-f0-9]+: 67 8f 2a f8 10 3c 65 00 00 00 00 67 00 00 00 bextr \$0x67,0x0\(,%r12d,2\),%r15
+[ ]*[a-f0-9]+: 8f ea f8 10 c0 00 00 00 00 bextr \$0x0,%rax,%rax
+[ ]*[a-f0-9]+: 67 8f ea f8 10 26 9b 53 00 00 bextr \$0x539b,\(%esi\),%rsp
+[ ]*[a-f0-9]+: 8f ca f8 10 08 ff ff ff 7f bextr \$0x7fffffff,\(%r8\),%rcx
+[ ]*[a-f0-9]+: 67 8f ea f8 10 04 3d ff ff ff 3f 01 00 00 00 bextr \$0x1,0x3fffffff\(,%edi,1\),%rax
+[ ]*[a-f0-9]+: 67 8f 8a f8 10 b4 30 84 dd ff ff 9e 00 00 00 bextr \$0x9e,-0x227c\(%r8d,%r14d,1\),%rsi
+[ ]*[a-f0-9]+: 8f ca f8 10 c7 64 c4 a6 02 bextr \$0x2a6c464,%r15,%rax
+[ ]*[a-f0-9]+: 67 8f 2a f8 10 4c 1f 02 04 00 00 00 bextr \$0x4,0x2\(%edi,%r11d,1\),%r9
+[ ]*[a-f0-9]+: 8f ea f8 10 ef 02 00 00 00 bextr \$0x2,%rdi,%rbp
+[ ]*[a-f0-9]+: 67 8f ca f8 10 14 16 fb 7e 1e 78 bextr \$0x781e7efb,\(%r14d,%edx,1\),%rdx
+[ ]*[a-f0-9]+: 8f 0a f8 10 ac 2b 68 db 00 00 39 40 cb 70 bextr \$0x70cb4039,0xdb68\(%r11,%r13,1\),%r13
+[ ]*[a-f0-9]+: 8f 4a f8 10 16 73 13 00 00 bextr \$0x1373,\(%r14\),%r10
+[ ]*[a-f0-9]+: 67 8f 2a f8 10 3c af 6d 55 00 00 bextr \$0x556d,\(%edi,%r13d,4\),%r15
+[ ]*[a-f0-9]+: 8f 4a f8 10 11 00 00 00 00 bextr \$0x0,\(%r9\),%r10
+[ ]*[a-f0-9]+: 8f 6a f8 10 1f ef ee ee 7b bextr \$0x7beeeeef,\(%rdi\),%r11
+[ ]*[a-f0-9]+: 8f e9 00 01 cc blcfill %esp,%r15d
+[ ]*[a-f0-9]+: 8f a9 68 01 0c a6 blcfill \(%rsi,%r12,4\),%edx
+[ ]*[a-f0-9]+: 67 8f e9 08 01 08 blcfill \(%eax\),%r14d
+[ ]*[a-f0-9]+: 8f a9 50 01 0c ad 00 00 00 00 blcfill 0x0\(,%r13,4\),%ebp
+[ ]*[a-f0-9]+: 67 8f c9 78 01 0e blcfill \(%r14d\),%eax
+[ ]*[a-f0-9]+: 8f c9 30 01 0b blcfill \(%r11\),%r9d
+[ ]*[a-f0-9]+: 8f a9 10 01 0c 45 ad de 00 00 blcfill 0xdead\(,%r8,2\),%r13d
+[ ]*[a-f0-9]+: 8f c9 00 01 cf blcfill %r15d,%r15d
+[ ]*[a-f0-9]+: 8f c9 40 01 ce blcfill %r14d,%edi
+[ ]*[a-f0-9]+: 8f e9 20 01 c8 blcfill %eax,%r11d
+[ ]*[a-f0-9]+: 8f c9 18 01 c9 blcfill %r9d,%r12d
+[ ]*[a-f0-9]+: 67 8f c9 60 01 4d 67 blcfill 0x67\(%r13d\),%ebx
+[ ]*[a-f0-9]+: 67 8f e9 00 01 0b blcfill \(%ebx\),%r15d
+[ ]*[a-f0-9]+: 67 8f a9 08 01 4c 19 0b blcfill 0xb\(%ecx,%r11d,1\),%r14d
+[ ]*[a-f0-9]+: 8f c9 78 01 8d 4a ff ff ff blcfill -0xb6\(%r13\),%eax
+[ ]*[a-f0-9]+: 8f c9 48 01 09 blcfill \(%r9\),%esi
+[ ]*[a-f0-9]+: 8f c9 f8 01 cf blcfill %r15,%rax
+[ ]*[a-f0-9]+: 8f c9 a0 01 cd blcfill %r13,%r11
+[ ]*[a-f0-9]+: 8f c9 e0 01 c8 blcfill %r8,%rbx
+[ ]*[a-f0-9]+: 67 8f c9 80 01 0f blcfill \(%r15d\),%r15
+[ ]*[a-f0-9]+: 67 8f c9 88 01 4d 00 blcfill 0x0\(%r13d\),%r14
+[ ]*[a-f0-9]+: 8f e9 b0 01 c8 blcfill %rax,%r9
+[ ]*[a-f0-9]+: 8f 89 e8 01 4c 24 0a blcfill 0xa\(%r12,%r12,1\),%rdx
+[ ]*[a-f0-9]+: 8f c9 98 01 ce blcfill %r14,%r12
+[ ]*[a-f0-9]+: 8f e9 a8 01 cf blcfill %rdi,%r10
+[ ]*[a-f0-9]+: 67 8f c9 90 01 0b blcfill \(%r11d\),%r13
+[ ]*[a-f0-9]+: 67 8f e9 b8 01 0c 15 25 c6 ff ff blcfill -0x39db\(,%edx,1\),%r8
+[ ]*[a-f0-9]+: 8f c9 d8 01 0c 34 blcfill \(%r12,%rsi,1\),%rsp
+[ ]*[a-f0-9]+: 67 8f 89 b8 01 4c 6d 00 blcfill 0x0\(%r13d,%r13d,2\),%r8
+[ ]*[a-f0-9]+: 8f e9 d0 01 08 blcfill \(%rax\),%rbp
+[ ]*[a-f0-9]+: 8f c9 80 01 09 blcfill \(%r9\),%r15
+[ ]*[a-f0-9]+: 8f c9 f0 01 cb blcfill %r11,%rcx
+[ ]*[a-f0-9]+: 8f c9 78 02 f7 blci %r15d,%eax
+[ ]*[a-f0-9]+: 8f e9 00 02 32 blci \(%rdx\),%r15d
+[ ]*[a-f0-9]+: 8f e9 28 02 f0 blci %eax,%r10d
+[ ]*[a-f0-9]+: 67 8f e9 38 02 37 blci \(%edi\),%r8d
+[ ]*[a-f0-9]+: 67 8f c9 68 02 75 00 blci 0x0\(%r13d\),%edx
+[ ]*[a-f0-9]+: 67 8f e9 20 02 32 blci \(%edx\),%r11d
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+[ ]*[a-f0-9]+: 8f e9 f8 01 fb t1mskc %rbx,%rax
+[ ]*[a-f0-9]+: 8f c9 f8 01 39 t1mskc \(%r9\),%rax
+[ ]*[a-f0-9]+: 67 8f c9 a8 01 38 t1mskc \(%r8d\),%r10
+[ ]*[a-f0-9]+: 8f e9 28 01 e3 tzmsk %ebx,%r10d
+[ ]*[a-f0-9]+: 8f c9 78 01 21 tzmsk \(%r9\),%eax
+[ ]*[a-f0-9]+: 8f e9 00 01 22 tzmsk \(%rdx\),%r15d
+[ ]*[a-f0-9]+: 8f e9 18 01 e5 tzmsk %ebp,%r12d
+[ ]*[a-f0-9]+: 8f c9 10 01 e2 tzmsk %r10d,%r13d
+[ ]*[a-f0-9]+: 8f c9 00 01 e7 tzmsk %r15d,%r15d
+[ ]*[a-f0-9]+: 8f 89 60 01 a4 0b 02 35 ff ff tzmsk -0xcafe\(%r11,%r9,1\),%ebx
+[ ]*[a-f0-9]+: 67 8f a9 68 01 64 2e 01 tzmsk 0x1\(%esi,%r13d,1\),%edx
+[ ]*[a-f0-9]+: 67 8f c9 08 01 23 tzmsk \(%r11d\),%r14d
+[ ]*[a-f0-9]+: 67 8f a9 70 01 24 a1 tzmsk \(%ecx,%r12d,4\),%ecx
+[ ]*[a-f0-9]+: 67 8f e9 30 01 20 tzmsk \(%eax\),%r9d
+[ ]*[a-f0-9]+: 8f e9 38 01 60 fa tzmsk -0x6\(%rax\),%r8d
+[ ]*[a-f0-9]+: 8f e9 48 01 e7 tzmsk %edi,%esi
+[ ]*[a-f0-9]+: 8f e9 00 01 e0 tzmsk %eax,%r15d
+[ ]*[a-f0-9]+: 8f e9 50 01 64 01 f1 tzmsk -0xf\(%rcx,%rax,1\),%ebp
+[ ]*[a-f0-9]+: 67 8f c9 20 01 27 tzmsk \(%r15d\),%r11d
+[ ]*[a-f0-9]+: 67 8f e9 e8 01 24 dd ad de 00 00 tzmsk 0xdead\(,%ebx,8\),%rdx
+[ ]*[a-f0-9]+: 67 8f e9 80 01 24 15 f8 ff ff ff tzmsk -0x8\(,%edx,1\),%r15
+[ ]*[a-f0-9]+: 8f e9 f8 01 e4 tzmsk %rsp,%rax
+[ ]*[a-f0-9]+: 67 8f c9 b8 01 21 tzmsk \(%r9d\),%r8
+[ ]*[a-f0-9]+: 8f e9 98 01 e0 tzmsk %rax,%r12
+[ ]*[a-f0-9]+: 8f c9 d0 01 e7 tzmsk %r15,%rbp
+[ ]*[a-f0-9]+: 8f 89 98 01 24 c9 tzmsk \(%r9,%r9,8\),%r12
+[ ]*[a-f0-9]+: 67 8f e9 90 01 24 9f tzmsk \(%edi,%ebx,4\),%r13
+[ ]*[a-f0-9]+: 8f e9 c0 01 e7 tzmsk %rdi,%rdi
+[ ]*[a-f0-9]+: 67 8f e9 f8 01 23 tzmsk \(%ebx\),%rax
+[ ]*[a-f0-9]+: 8f e9 d8 01 26 tzmsk \(%rsi\),%rsp
+[ ]*[a-f0-9]+: 8f c9 f0 01 a0 02 35 ff ff tzmsk -0xcafe\(%r8\),%rcx
+[ ]*[a-f0-9]+: 67 8f c9 88 01 a4 02 98 3c 00 00 tzmsk 0x3c98\(%r10d,%eax,1\),%r14
+[ ]*[a-f0-9]+: 67 8f c9 80 01 23 tzmsk \(%r11d\),%r15
+[ ]*[a-f0-9]+: 8f e9 c8 01 e6 tzmsk %rsi,%rsi
+[ ]*[a-f0-9]+: 8f a9 b0 01 24 05 53 21 ff ff tzmsk -0xdead\(,%r8,1\),%r9
diff --git a/gas/testsuite/gas/i386/x86-64-tbm.s b/gas/testsuite/gas/i386/x86-64-tbm.s
new file mode 100644
index 0000000..e1bbb9d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-tbm.s
@@ -0,0 +1,327 @@
+
+ .allow_index_reg
+ .text
+
+_start:
+
+ BEXTR $0x0,%eax,%r15d
+ BEXTR $0x4DF1,%r15d,%r10d
+ BEXTR $0x2DA55E92,%r13d,%r14d
+ BEXTR $0x7FFFFFFF,0x6(%r13d,%r15d,2),%eax
+ BEXTR $0x251EF761,%r11d,%ebp
+ BEXTR $0x2B39,(%rdi,%rdx,8),%r15d
+ BEXTR $0x92,0xDEAD(,%r14),%r9d
+ BEXTR $0x6887,(%r13),%esi
+ BEXTR $0xD,(%r9d),%ecx
+ BEXTR $0x2B,0x40D8(,%rax),%ebx
+ BEXTR $0xEA2D,(%r8),%r8d
+ BEXTR $0x6C,(%r13d),%r12d
+ BEXTR $0x9E3B,0x8C8F(,%rcx),%r11d
+ BEXTR $0xF,(%r10d,%eax),%esp
+ BEXTR $0xDEAD,-0x0(,%r9d,8),%edi
+ BEXTR $0xCAFE,%r8d,%eax
+ BEXTR $0x7D263BB9,0x10BC(%r9),%r8
+ BEXTR $0x67,(,%r12d,2),%r15
+ BEXTR $0x0,%rax,%rax
+ BEXTR $0x539B,(%esi),%rsp
+ BEXTR $0x7FFFFFFF,(%r8),%rcx
+ BEXTR $0x1,0x3FFFFFFF(,%edi),%rax
+ BEXTR $0x9E,-0x227C(%r8d,%r14d),%rsi
+ BEXTR $0x2A6C464,%r15,%rax
+ BEXTR $0x4,0x2(%edi,%r11d,1),%r9
+ BEXTR $0x2,%rdi,%rbp
+ BEXTR $0x781E7EFB,(%r14d,%edx,1),%rdx
+ BEXTR $0x70CB4039,0xDB68(%r11,%r13),%r13
+ BEXTR $0x1373,(%r14),%r10
+ BEXTR $0x556D,(%edi,%r13d,4),%r15
+ BEXTR $0x0,(%r9),%r10
+ BEXTR $0x7BEEEEEF,(%rdi),%r11
+ BLCFILL %esp,%r15d
+ BLCFILL (%rsi,%r12,4),%edx
+ BLCFILL (%eax),%r14d
+ BLCFILL (,%r13,4),%ebp
+ BLCFILL (%r14d),%eax
+ BLCFILL (%r11),%r9d
+ BLCFILL 0xDEAD(,%r8,2),%r13d
+ BLCFILL %r15d,%r15d
+ BLCFILL %r14d,%edi
+ BLCFILL %eax,%r11d
+ BLCFILL %r9d,%r12d
+ BLCFILL 0x67(%r13d),%ebx
+ BLCFILL (%ebx),%r15d
+ BLCFILL 0xB(%ecx,%r11d),%r14d
+ BLCFILL -0xB6(%r13),%eax
+ BLCFILL (%r9),%esi
+ BLCFILL %r15,%rax
+ BLCFILL %r13,%r11
+ BLCFILL %r8,%rbx
+ BLCFILL (%r15d),%r15
+ BLCFILL (%r13d),%r14
+ BLCFILL %rax,%r9
+ BLCFILL 0xA(%r12,%r12,1),%rdx
+ BLCFILL %r14,%r12
+ BLCFILL %rdi,%r10
+ BLCFILL (%r11d),%r13
+ BLCFILL -0x39DB(,%edx),%r8
+ BLCFILL (%r12,%rsi),%rsp
+ BLCFILL (%r13d,%r13d,2),%r8
+ BLCFILL (%rax),%rbp
+ BLCFILL (%r9),%r15
+ BLCFILL %r11,%rcx
+ BLCI %r15d,%eax
+ BLCI (%rdx),%r15d
+ BLCI %eax,%r10d
+ BLCI (%edi),%r8d
+ BLCI (%r13d),%edx
+ BLCI (%edx),%r11d
+ BLCI 0x937(,%eax),%r12d
+ BLCI (%r9),%ecx
+ BLCI (%r9d),%esp
+ BLCI %edx,%esi
+ BLCI %ebp,%r14d
+ BLCI %ebx,%eax
+ BLCI (%rax),%r8d
+ BLCI (,%r14d,2),%edi
+ BLCI (%rbx),%eax
+ BLCI 0x434CA331(%r9d,%r14d),%r9d
+ BLCI (%ebx),%r11
+ BLCI (%r15),%rax
+ BLCI (%r12d,%ebx,8),%r15
+ BLCI %r15,%rbp
+ BLCI -0x0(%ebx,%esi),%rsp
+ BLCI %r12,%rcx
+ BLCI (%r9),%rdi
+ BLCI (%r12d,%edi,1),%rbx
+ BLCI 0x5B19(,%rdx,8),%r15
+ BLCI (,%eax,8),%r10
+ BLCI (%rbx),%r8
+ BLCI -0xF5(%eax,%edx,2),%r9
+ BLCI (%r13),%r14
+ BLCI %rbp,%rax
+ BLCI (%eax),%r13
+ BLCI (%r12),%rdx
+ BLCIC (%r14d,%eax,8),%r15d
+ BLCIC %r15d,%eax
+ BLCIC (%r9),%r8d
+ BLCIC (%r9,%rbx,2),%r9d
+ BLCIC (%ebx),%esi
+ BLCIC -0x2(,%eax),%ebp
+ BLCIC (%rax),%ebx
+ BLCIC (%r11),%edi
+ BLCIC %eax,%r11d
+ BLCIC (%r14),%r12d
+ BLCIC %r11d,%eax
+ BLCIC 0x141AD0A7(,%r11),%r15d
+ BLCIC (%rax,%r9,4),%r13d
+ BLCIC (%rbx),%r15d
+ BLCIC (%r15d,%r15d),%r10d
+ BLCIC (%r9d),%edx
+ BLCIC 0x59D3CBB3(,%r13d,1),%rcx
+ BLCIC %r14,%rax
+ BLCIC (%r12d),%r15
+ BLCIC %rax,%r14
+ BLCIC %r15,%rbp
+ BLCIC (%rbx),%rsp
+ BLCIC %rbx,%rdx
+ BLCIC %r8,%rdi
+ BLCIC (%r9),%rsi
+ BLCIC 0xDBDB(,%rax,8),%rdi
+ BLCIC %r10,%rbx
+ BLCIC (%ebx),%r11
+ BLCIC %r13,%r9
+ BLCIC (%r8),%rax
+ BLCIC 0xDEAD(%r10,%r10,1),%r12
+ BLCIC (%edx,%eax),%rcx
+ BLCMSK (%ecx),%r15d
+ BLCMSK %ebp,%eax
+ BLCMSK (%ebx),%edi
+ BLCMSK %eax,%edx
+ BLCMSK (,%r10,8),%r13d
+ BLCMSK (%r9),%r9d
+ BLCMSK (%r10),%r12d
+ BLCMSK %ecx,%ebx
+ BLCMSK (%edx),%eax
+ BLCMSK %esi,%r11d
+ BLCMSK (,%r14,4),%r15d
+ BLCMSK %r15d,%eax
+ BLCMSK 0xF35F(%r14d),%r14d
+ BLCMSK (%r8d,%esi,1),%r8d
+ BLCMSK (%r12,%rdx),%esp
+ BLCMSK (%r8d),%r10d
+ BLCMSK 0x0(,%r13d),%r12
+ BLCMSK %r15,%rbx
+ BLCMSK %rax,%r15
+ BLCMSK 0x3(,%r9d,1),%r8
+ BLCMSK -0xCAFE(%r9,%r15,2),%rbp
+ BLCMSK (%r13),%rsp
+ BLCMSK (%rdx),%rax
+ BLCMSK (%r12),%r13
+ BLCMSK -0x7(,%rdx,8),%rdx
+ BLCMSK (%r11),%r14
+ BLCMSK %r14,%r9
+ BLCMSK (%rcx),%r11
+ BLCMSK (%r14d),%rax
+ BLCMSK (,%rax,8),%rdi
+ BLCMSK (%r15d),%r13
+ BLCMSK (%ebx,%esi),%r14
+ BLCS (%rax),%r15d
+ BLCS 0x1(,%r8d,1),%r8d
+ BLCS %r10d,%ecx
+ BLCS %r15d,%r10d
+ BLCS %r11d,%eax
+ BLCS -0x7E972365(%ecx),%edi
+ BLCS (%esi),%r14d
+ BLCS -0x3(%r10),%r11d
+ BLCS (%rdi),%esp
+ BLCS (%r15d),%ebx
+ BLCS (%r9,%rsi,4),%r13d
+ BLCS 0x0(%r9,%rbx,1),%r9d
+ BLCS (%eax,%ecx),%r15d
+ BLCS %ebx,%esi
+ BLCS %esi,%eax
+ BLCS %edi,%r12d
+ BLCS %rdi,%rax
+ BLCS (%rax),%r12
+ BLCS %r15,%r15
+ BLCS %r10,%rcx
+ BLCS (%eax),%r13
+ BLCS %rax,%r8
+ BLCS -0x1(%edx),%rdi
+ BLCS %rbx,%r11
+ BLCS (,%eax,2),%rsp
+ BLCS (%r9,%r13),%r10
+ BLCS 0x1DCF(,%r8d,1),%r14
+ BLCS (,%r15d,4),%r15
+ BLCS (%r9),%rbp
+ BLCS (%r13d,%eax),%rdx
+ BLCS %r12,%rsp
+ BLCS (%rdi),%rbx
+ BLSFILL (%esi),%edx
+ BLSFILL (%r9),%eax
+ BLSFILL (%ebx),%r15d
+ BLSFILL %eax,%r11d
+ BLSFILL (%r12),%r8d
+ BLSFILL -0x5582(,%r9d),%r15d
+ BLSFILL %esp,%eax
+ BLSFILL (,%r12d,2),%ebp
+ BLSFILL (%r8d),%ebx
+ BLSFILL (%eax),%esp
+ BLSFILL 0x4F03(,%r11),%r12d
+ BLSFILL 0xF(,%r10d),%eax
+ BLSFILL (%r15d),%edi
+ BLSFILL 0x228F(,%rsi,1),%ecx
+ BLSFILL (%ecx),%esi
+ BLSFILL %r8d,%r13d
+ BLSFILL -0xC(,%eax,4),%r15
+ BLSFILL %rax,%r12
+ BLSFILL %rdx,%rax
+ BLSFILL (%r9),%rbp
+ BLSFILL (%edi),%rbx
+ BLSFILL %r15,%r9
+ BLSFILL %rbx,%rsp
+ BLSFILL (%r15),%rax
+ BLSFILL 0x56B9(%edi,%edi),%r10
+ BLSFILL -0x2BD1(%r12d,%esi,4),%rcx
+ BLSFILL (%r11),%rsp
+ BLSFILL %r13,%r8
+ BLSFILL (%ebx,%eax,2),%rax
+ BLSFILL (%ebx),%rax
+ BLSFILL (%rbx,%rdx),%r11
+ BLSFILL 0x2FDC(%r13),%rsi
+ BLSIC %r11d,%r15d
+ BLSIC -0x799F(,%rsi),%ebp
+ BLSIC %r15d,%eax
+ BLSIC -0x0(%rax,%r10,1),%ecx
+ BLSIC %eax,%r10d
+ BLSIC (%r13d),%r9d
+ BLSIC (%r9),%ebx
+ BLSIC (%ebx),%esp
+ BLSIC (%r12d),%r11d
+ BLSIC 0xBCFE(,%rdi,1),%edx
+ BLSIC (%r14d),%edi
+ BLSIC 0x78EC(,%r13d),%r15d
+ BLSIC (%r11d),%esi
+ BLSIC (%r10),%r14d
+ BLSIC (%r9d),%r15d
+ BLSIC %r10d,%r15d
+ BLSIC %r15,%rax
+ BLSIC 0x67(,%rax),%r9
+ BLSIC (%r8d,%r12d),%rdx
+ BLSIC (%r15d),%r15
+ BLSIC %r9,%rcx
+ BLSIC %r10,%rdi
+ BLSIC 0x3FFFFFFF(,%r8),%rbx
+ BLSIC %rdx,%r15
+ BLSIC (%rax),%rsi
+ BLSIC 0x0(%r15d),%rax
+ BLSIC (%rbx),%r15
+ BLSIC %rax,%r8
+ BLSIC (%ebx),%rax
+ BLSIC %rcx,%r14
+ BLSIC (%r15d,%eax,1),%rsi
+ BLSIC %r13,%r12
+ T1MSKC -0x3(%rsi),%r15d
+ T1MSKC %r15d,%r12d
+ T1MSKC (%r12),%r9d
+ T1MSKC %esi,%eax
+ T1MSKC -0x2(%r10d),%esp
+ T1MSKC (,%eax,2),%r13d
+ T1MSKC %eax,%esi
+ T1MSKC (%r12d),%eax
+ T1MSKC 0xF59C(,%rbx),%r10d
+ T1MSKC (,%eax,4),%r11d
+ T1MSKC (%ebx),%r8d
+ T1MSKC %edi,%ebx
+ T1MSKC (%edx),%r14d
+ T1MSKC (%r11d),%r15d
+ T1MSKC (%esi),%ecx
+ T1MSKC (%r9,%r13),%edi
+ T1MSKC 0x3FFFFFFF(%r14),%rsp
+ T1MSKC %rax,%rax
+ T1MSKC (%r8),%rbx
+ T1MSKC (%r12d,%edi),%rdi
+ T1MSKC %r11,%rcx
+ T1MSKC (%r13),%r14
+ T1MSKC 0xDEAD(,%eax,8),%rdx
+ T1MSKC %r15,%r15
+ T1MSKC (%r15),%rbp
+ T1MSKC %rsp,%r9
+ T1MSKC (%rdx),%rsi
+ T1MSKC %r10,%r10
+ T1MSKC (%r9d),%r13
+ T1MSKC %rbx,%rax
+ T1MSKC (%r9),%rax
+ T1MSKC (%r8d),%r10
+ TZMSK %ebx,%r10d
+ TZMSK (%r9),%eax
+ TZMSK (%rdx),%r15d
+ TZMSK %ebp,%r12d
+ TZMSK %r10d,%r13d
+ TZMSK %r15d,%r15d
+ TZMSK -0xCAFE(%r11,%r9,1),%ebx
+ TZMSK 0x1(%esi,%r13d),%edx
+ TZMSK (%r11d),%r14d
+ TZMSK (%ecx,%r12d,4),%ecx
+ TZMSK (%eax),%r9d
+ TZMSK -0x6(%rax),%r8d
+ TZMSK %edi,%esi
+ TZMSK %eax,%r15d
+ TZMSK -0xF(%rcx,%rax,1),%ebp
+ TZMSK (%r15d),%r11d
+ TZMSK 0xDEAD(,%ebx,8),%rdx
+ TZMSK -0x8(,%edx),%r15
+ TZMSK %rsp,%rax
+ TZMSK (%r9d),%r8
+ TZMSK %rax,%r12
+ TZMSK %r15,%rbp
+ TZMSK (%r9,%r9,8),%r12
+ TZMSK (%edi,%ebx,4),%r13
+ TZMSK %rdi,%rdi
+ TZMSK (%ebx),%rax
+ TZMSK (%rsi),%rsp
+ TZMSK -0xCAFE(%r8),%rcx
+ TZMSK 0x3C98(%r10d,%eax),%r14
+ TZMSK (%r11d),%r15
+ TZMSK %rsi,%rsi
+ TZMSK -0xDEAD(,%r8),%r9
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8f1b4bd..d67d32f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,33 @@
2010-12-20 Quentin Neill <quentin.neill@amd.com>
+ * i386-dis.c (REG_XOP_TBM_01): New.
+ (REG_XOP_TBM_02): New.
+ (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
+ (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
+ entries, and add bextr instruction.
+ * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
+ (cpu_flags): Add CpuTBM.
+ * i386-opc.h (CpuTBM) New.
+ (i386_cpu_flags): Add bit cputbm.
+
+ * i386-opc.tbl (bextr): Added.
+ (bextr): Added.
+ (blcfill): Added.
+ (blci): Added.
+ (blcic): Added.
+ (blcmsk): Added.
+ (blcs): Added.
+ (blsfill): Added.
+ (blsic): Added.
+ (t1mskc): Added.
+ (tzmsk): Added.
+
+ * i386-init.h: Regenerated.
+
+ * i386-tbl.h: Regenerated
+
+2010-12-20 Quentin Neill <quentin.neill@amd.com>
+
* i386-dis.c (REG_XOP_BMI_F3): New.
(PREFIX_BMI_F30F): New.
(dis386_twobyte): Redirect to PREFIX_BMI_F30F entry.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 30ea470..5640209 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -600,7 +600,9 @@ enum
REG_VEX_0FAE,
REG_XOP_LWPCB,
REG_XOP_LWP,
- REG_XOP_BMI_F3
+ REG_XOP_BMI_F3,
+ REG_XOP_TBM_01,
+ REG_XOP_TBM_02,
};
enum
@@ -2768,6 +2770,28 @@ static const struct dis386 reg_table[][8] = {
{ "blsmsk", { { OP_LWP_E, 0 }, Ev } },
{ "blsi", { { OP_LWP_E, 0 }, Ev } },
},
+ /* REG_XOP_TBM_01 */
+ {
+ { Bad_Opcode },
+ { "blcfill", { { OP_LWP_E, 0 }, Ev } },
+ { "blsfill", { { OP_LWP_E, 0 }, Ev } },
+ { "blcs", { { OP_LWP_E, 0 }, Ev } },
+ { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
+ { "blcic", { { OP_LWP_E, 0 }, Ev } },
+ { "blsic", { { OP_LWP_E, 0 }, Ev } },
+ { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
+ },
+ /* REG_XOP_TBM_02 */
+ {
+ { Bad_Opcode },
+ { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "blci", { { OP_LWP_E, 0 }, Ev } },
+ },
+
};
static const struct dis386 prefix_table[][4] = {
@@ -6698,8 +6722,8 @@ static const struct dis386 xop_table[][256] = {
{
/* 00 */
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { REG_TABLE (REG_XOP_TBM_01) },
+ { REG_TABLE (REG_XOP_TBM_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -7006,7 +7030,7 @@ static const struct dis386 xop_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { Bad_Opcode },
+ { "bextr", { Gv, Ev, Iq } },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index c4ed21f..63e0b8d 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,6 +140,8 @@ static initializer cpu_flag_init[] =
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
{ "CPU_LWP_FLAGS",
"CpuLWP" },
+ { "CPU_TBM_FLAGS",
+ "CpuTBM" },
{ "CPU_BMI_FLAGS",
"CpuBMI" },
{ "CPU_MOVBE_FLAGS",
@@ -322,6 +324,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuFMA4),
BITFIELD (CpuXOP),
BITFIELD (CpuLWP),
+ BITFIELD (CpuTBM),
BITFIELD (CpuBMI),
BITFIELD (CpuLM),
BITFIELD (CpuMovbe),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 43c0d14..2208b83 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,6 +110,8 @@ enum
CpuXOP,
/* LWP support required */
CpuLWP,
+ /* TBM support required */
+ CpuTBM,
/* BMI support required */
CpuBMI,
/* MOVBE Instruction support required */
@@ -188,6 +190,7 @@ typedef union i386_cpu_flags
unsigned int cpufma4:1;
unsigned int cpuxop:1;
unsigned int cpulwp:1;
+ unsigned int cputbm:1;
unsigned int cpubmi:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 23eb2f2..3bff501 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,6 +2733,28 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+// TBM instructions
+bextr, 3, 0x10, None, 1, CpuTBM, Modrm|VexOpcode=5|VexW=1|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+bextr, 3, 0x10, None, 1, CpuTBM, Modrm|VexOpcode=5|VexW=2|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm32|Imm32S, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|ModrmRegExt|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+
// BMI instructions
andn, 3, 0xF2, None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32, Reg32 }
andn, 3, 0xF2, None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64, Reg64 }
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