[PATCH,ppc] prohibit string instructions on processors that don't support them

[Nathan Froyd]

On Wed, Aug 25, 2010 at 03:22:23PM -0500, Peter Bergner wrote:
> On Wed, 2010-08-25 at 12:40 -0700, Nathan Froyd wrote:
> > Processors in the E500 family (both the SPE and oddly-named e500mc*
> > variety) do not support load/store string instructions.  This patch adds
> > a PPC_OPCODE_STRING flag for marking these instructions so the assembler
> > can give appropriate error messages when attempting to assemble such
> > instructions.
> 
> Wouldn't it be easier to just add the appropriate flags to the deprecated
> field to disable the string ops for the cpus that don't want them
> similar to how we disable lwsync for E500?
> 
>   {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},

Oh my, yes, this is easier.  Thanks for pointing that out.

How about this patch?

-Nathan

opcodes/
	* ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
	on E500 and E500MC.

Index: opcodes/ppc-opc.c
===================================================================
--- opcodes/ppc-opc.c
+++ opcodes/ppc-opc.c
@@ -4420,7 +4420,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"ldbrx",	X(31,532),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RT, RA0, RB}},
 
-{"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
+{"lswx",	X(31,533),	X_MASK,      PPCCOM,	E500|E500MC,	{RT, RA0, RB}},
 {"lsx",		X(31,533),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"lwbrx",	X(31,534),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
@@ -4466,7 +4466,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"mfsr",	X(31,595), XRB_MASK|(1<<20), COM,	NON32,  	{RT, SR}},
 
-{"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
+{"lswi",	X(31,597),	X_MASK,      PPCCOM,	E500|E500MC,	{RT, RA0, NB}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
 
 {"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	E500,		{0}},
@@ -4517,7 +4517,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"stdbrx",	X(31,660),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RS, RA0, RB}},
 
-{"stswx",	X(31,661),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
+{"stswx",	X(31,661),	X_MASK,      PPCCOM,	E500|E500MC,	{RS, RA0, RB}},
 {"stsx",	X(31,661),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
 
 {"stwbrx",	X(31,662),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
@@ -4559,7 +4559,7 @@ const struct powerpc_opcode powerpc_opco
 {"addzeo.",	XO(31,202,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
 {"azeo.",	XO(31,202,1,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"stswi",	X(31,725),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, NB}},
+{"stswi",	X(31,725),	X_MASK,      PPCCOM,	E500|E500MC,	{RS, RA0, NB}},
 {"stsi",	X(31,725),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, NB}},
 
 {"sthcx.",	XRC(31,726,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},