Patch to put i386_insn into header file.
Martin Thuresson
martint@google.com
Sat Sep 26 05:14:00 GMT 2009
This patch moves the definition of i386_insn (and other related
types) to tc-i386.h in order to make it possible to reuse in
other files.
Built and tested with target x86_64-linux.
Thanks,
Martin
-------------- next part --------------
2009-09-25 Martin Thuresson <martint@google.com>
* gas/config/tc-i386.c: (WAIT_PREFIX, SEG_PREFIX, ADDR_PREFIX)
(DATA_PREFIX, LOCKREP_PREFIX, REX_PREFIX, MAX_PREFIXES)
(modrm_byte, rex_byte, sib_byte, vex_prefix, union i386_op, struct
_i386_insn, i386_insn, enum flag_code): Move to header.
* gas/config/tc-i386.c: (WAIT_PREFIX, SEG_PREFIX, ADDR_PREFIX)
(DATA_PREFIX, LOCKREP_PREFIX, REX_PREFIX, MAX_PREFIXES)
(modrm_byte, rex_byte, sib_byte, vex_prefix, union i386_op, struct
_i386_insn, i386_insn, enum flag_code): Added.
-------------- next part --------------
Index: gas/config/tc-i386.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i386.c,v
retrieving revision 1.398
diff -u -u -p -r1.398 tc-i386.c
--- gas/config/tc-i386.c 24 Sep 2009 16:37:09 -0000 1.398
+++ gas/config/tc-i386.c 26 Sep 2009 04:28:53 -0000
@@ -55,19 +55,6 @@
#endif
#endif
-/* Prefixes will be emitted in the order defined below.
- WAIT_PREFIX must be the first prefix since FWAIT is really is an
- instruction, and so must come before any prefixes.
- The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
- LOCKREP_PREFIX. */
-#define WAIT_PREFIX 0
-#define SEG_PREFIX 1
-#define ADDR_PREFIX 2
-#define DATA_PREFIX 3
-#define LOCKREP_PREFIX 4
-#define REX_PREFIX 5 /* must come last. */
-#define MAX_PREFIXES 6 /* max prefixes per opcode */
-
/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
@@ -102,26 +89,6 @@ typedef struct
}
templates;
-/* 386 operand encoding bytes: see 386 book for details of this. */
-typedef struct
-{
- unsigned int regmem; /* codes register or memory operand */
- unsigned int reg; /* codes register operand (or extended opcode) */
- unsigned int mode; /* how to interpret regmem & reg */
-}
-modrm_byte;
-
-/* x86-64 extension prefix. */
-typedef int rex_byte;
-
-/* 386 opcode byte to code indirect addressing. */
-typedef struct
-{
- unsigned base;
- unsigned index;
- unsigned scale;
-}
-sib_byte;
/* x86 arch names, types and features */
typedef struct
@@ -181,85 +148,6 @@ static void handle_large_common (int sma
static const char *default_arch = DEFAULT_ARCH;
-/* VEX prefix. */
-typedef struct
-{
- /* VEX prefix is either 2 byte or 3 byte. */
- unsigned char bytes[3];
- unsigned int length;
- /* Destination or source register specifier. */
- const reg_entry *register_specifier;
-} vex_prefix;
-
-/* 'md_assemble ()' gathers together information and puts it into a
- i386_insn. */
-
-union i386_op
- {
- expressionS *disps;
- expressionS *imms;
- const reg_entry *regs;
- };
-
-struct _i386_insn
- {
- /* TM holds the template for the insn were currently assembling. */
- insn_template tm;
-
- /* SUFFIX holds the instruction size suffix for byte, word, dword
- or qword, if given. */
- char suffix;
-
- /* OPERANDS gives the number of given operands. */
- unsigned int operands;
-
- /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
- of given register, displacement, memory operands and immediate
- operands. */
- unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
-
- /* TYPES [i] is the type (see above #defines) which tells us how to
- use OP[i] for the corresponding operand. */
- i386_operand_type types[MAX_OPERANDS];
-
- /* Displacement expression, immediate expression, or register for each
- operand. */
- union i386_op op[MAX_OPERANDS];
-
- /* Flags for operands. */
- unsigned int flags[MAX_OPERANDS];
-#define Operand_PCrel 1
-
- /* Relocation type for operand */
- enum bfd_reloc_code_real reloc[MAX_OPERANDS];
-
- /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
- the base index byte below. */
- const reg_entry *base_reg;
- const reg_entry *index_reg;
- unsigned int log2_scale_factor;
-
- /* SEG gives the seg_entries of this insn. They are zero unless
- explicit segment overrides are given. */
- const seg_entry *seg[2];
-
- /* PREFIX holds all the given prefix opcodes (usually null).
- PREFIXES is the number of prefix opcodes. */
- unsigned int prefixes;
- unsigned char prefix[MAX_PREFIXES];
-
- /* RM and SIB are the modrm byte and the sib byte where the
- addressing modes of this insn are encoded. */
- modrm_byte rm;
- rex_byte rex;
- sib_byte sib;
- vex_prefix vex;
-
- /* Swap operand in encoding. */
- unsigned int swap_operand : 1;
- };
-
-typedef struct _i386_insn i386_insn;
/* List of chars besides those in app.c:symbol_chars that can start an
operand. Used to prevent the scrubber eating vital white-space. */
@@ -354,14 +242,6 @@ static expressionS im_expressions[MAX_IM
/* Current operand we are working on. */
static int this_operand = -1;
-/* We support four different modes. FLAG_CODE variable is used to distinguish
- these. */
-
-enum flag_code {
- CODE_32BIT,
- CODE_16BIT,
- CODE_64BIT };
-
static enum flag_code flag_code;
static unsigned int object_64bit;
static int use_rela_relocations = 0;
Index: gas/config/tc-i386.h
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i386.h,v
retrieving revision 1.113
diff -u -u -p -r1.113 tc-i386.h
--- gas/config/tc-i386.h 24 Sep 2009 14:36:47 -0000 1.113
+++ gas/config/tc-i386.h 26 Sep 2009 04:28:53 -0000
@@ -293,6 +293,131 @@ void tc_pe_dwarf2_emit_offset (symbolS *
#endif /* TE_PE */
+/* Prefixes will be emitted in the order defined below.
+ WAIT_PREFIX must be the first prefix since FWAIT is really is an
+ instruction, and so must come before any prefixes.
+ The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
+ LOCKREP_PREFIX. */
+#define WAIT_PREFIX 0
+#define SEG_PREFIX 1
+#define ADDR_PREFIX 2
+#define DATA_PREFIX 3
+#define LOCKREP_PREFIX 4
+#define REX_PREFIX 5 /* must come last. */
+#define MAX_PREFIXES 6 /* max prefixes per opcode */
+
+/* 386 operand encoding bytes: see 386 book for details of this. */
+typedef struct
+{
+ unsigned int regmem; /* codes register or memory operand */
+ unsigned int reg; /* codes register operand (or extended opcode) */
+ unsigned int mode; /* how to interpret regmem & reg */
+}
+modrm_byte;
+
+
+/* x86-64 extension prefix. */
+typedef int rex_byte;
+
+/* 386 opcode byte to code indirect addressing. */
+typedef struct
+{
+ unsigned base;
+ unsigned index;
+ unsigned scale;
+}
+sib_byte;
+
+/* VEX prefix. */
+typedef struct
+{
+ /* VEX prefix is either 2 byte or 3 byte. */
+ unsigned char bytes[3];
+ unsigned int length;
+ /* Destination or source register specifier. */
+ const reg_entry *register_specifier;
+} vex_prefix;
+
+
+/* 'md_assemble ()' gathers together information and puts it into a
+ i386_insn. */
+
+union i386_op
+ {
+ expressionS *disps;
+ expressionS *imms;
+ const reg_entry *regs;
+ };
+
+struct _i386_insn
+ {
+ /* TM holds the template for the insn were currently assembling. */
+ insn_template tm;
+
+ /* SUFFIX holds the instruction size suffix for byte, word, dword
+ or qword, if given. */
+ char suffix;
+
+ /* OPERANDS gives the number of given operands. */
+ unsigned int operands;
+
+ /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
+ of given register, displacement, memory operands and immediate
+ operands. */
+ unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
+
+ /* TYPES [i] is the type (see above #defines) which tells us how to
+ use OP[i] for the corresponding operand. */
+ i386_operand_type types[MAX_OPERANDS];
+
+ /* Displacement expression, immediate expression, or register for each
+ operand. */
+ union i386_op op[MAX_OPERANDS];
+
+ /* Flags for operands. */
+ unsigned int flags[MAX_OPERANDS];
+#define Operand_PCrel 1
+
+ /* Relocation type for operand */
+ enum bfd_reloc_code_real reloc[MAX_OPERANDS];
+
+ /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
+ the base index byte below. */
+ const reg_entry *base_reg;
+ const reg_entry *index_reg;
+ unsigned int log2_scale_factor;
+
+ /* SEG gives the seg_entries of this insn. They are zero unless
+ explicit segment overrides are given. */
+ const seg_entry *seg[2];
+
+ /* PREFIX holds all the given prefix opcodes (usually null).
+ PREFIXES is the number of prefix opcodes. */
+ unsigned int prefixes;
+ unsigned char prefix[MAX_PREFIXES];
+
+ /* RM and SIB are the modrm byte and the sib byte where the
+ addressing modes of this insn are encoded. */
+ modrm_byte rm;
+ rex_byte rex;
+ sib_byte sib;
+ vex_prefix vex;
+
+ /* Swap operand in encoding. */
+ unsigned int swap_operand : 1;
+ };
+
+typedef struct _i386_insn i386_insn;
+
+/* We support four different modes. FLAG_CODE variable is used to distinguish
+ these. */
+
+enum flag_code {
+ CODE_32BIT,
+ CODE_16BIT,
+ CODE_64BIT };
+
+
/* X_add_symbol:X_op_symbol (Intel mode only) */
#define O_full_ptr O_md2
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