[PATCH bfin] Four pseudo instructions
Jie Zhang
jie.zhang@analog.com
Fri Sep 4 04:38:00 GMT 2009
Those pseudo instructions are mainly for ADI internal use. This patch
adds support of HLT pseudo instruction. It also changes codings of other
three pseudo instructons: DBGA, DBGAH and DBGAL such that more registers
can be asserted.
Previous encoding:
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
dbgop
0: DBGA (Dregs_lo, uimm16);
1: DBGA (Dregs_hi, uimm16);
2: DBGAL (Dregs, uimm16);
3: DBGAH (Dregs, uimm16);
4-7: reserved.
This encoding only allows Dregs to be asserted. With this patch, the new
encoding is
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
This new encoding adds register group, thus all registers can be encoded.
dbgop
0: DBGA (D/P/I/L/M/Bregs_lo, uimm16);
1: DBGA (D/P/I/L/M/Bregs_hi, uimm16);
2: DBGAL (allregs, uimm16);
3: DBGAH (allregs, uimm16);
Committed.
Jie
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