PATCH: Allow DMB, DSB, and ISB on ARMv6-M cores

[Mark Mitchell]

ARMv6-M cores have support for the (32-bit) memory barrier
instructions.  But, GAS was issuing errors about not being abled to
honor the requested instruction size when attempting to assemble them.
This patch, approved by Paul Brook offline, fixes the problem.

Applied.

--
Mark Mitchell
CodeSourcery
mark@codesourcery.com
(650) 331-3385 x713

2009-03-01  Mark Mitchell  <mark@codesourcery.com>

	* config/tc-arm.c (md_assemble): Allow barrier instructions on
	ARMv6-M cores.

2009-03-01  Mark Mitchell  <mark@codesourcery.com>

	* gas/arm/archv6m.s: Add dmb, dsb, and isb.
	* gas/arm/archv6m.d: Likewise.

Index: config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.376
diff -c -5 -p -r1.376 tc-arm.c
*** config/tc-arm.c	24 Feb 2009 04:30:28 -0000	1.376
--- config/tc-arm.c	2 Mar 2009 00:20:31 -0000
*************** md_assemble (char *str)
*** 14745,14755 ****
        if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
  	{
  	  /* Implicit require narrow instructions on Thumb-1.  This avoids
  	     relaxation accidentally introducing Thumb-2 instructions.  */
  	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
! 	      && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
  	    inst.size_req = 2;
  	}
  
        /* Check conditional suffixes.  */
        if (current_it_mask)
--- 14745,14756 ----
        if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
  	{
  	  /* Implicit require narrow instructions on Thumb-1.  This avoids
  	     relaxation accidentally introducing Thumb-2 instructions.  */
  	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
! 	      && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
! 		   || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
  	    inst.size_req = 2;
  	}
  
        /* Check conditional suffixes.  */
        if (current_it_mask)
*************** md_assemble (char *str)
*** 14803,14813 ****
  	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
  	 anything other than bl/blx and v6-M instructions.
  	 This is overly pessimistic for relaxable instructions.  */
        if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
  	   || inst.relax)
! 	  && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
  	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
  				arm_ext_v6t2);
      }
    else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
      {
--- 14804,14815 ----
  	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
  	 anything other than bl/blx and v6-M instructions.
  	 This is overly pessimistic for relaxable instructions.  */
        if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
  	   || inst.relax)
! 	  && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
! 	       || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
  	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
  				arm_ext_v6t2);
      }
    else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
      {
Index: testsuite/gas/arm/archv6m.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/archv6m.d,v
retrieving revision 1.2
diff -c -5 -p -r1.2 archv6m.d
*** testsuite/gas/arm/archv6m.d	15 Jan 2009 12:33:46 -0000	1.2
--- testsuite/gas/arm/archv6m.d	2 Mar 2009 00:20:31 -0000
*************** Disassembly of section .text:
*** 11,15 ****
--- 11,18 ----
  0[0-9a-f]+ <[^>]+> bf20      	wfe
  0[0-9a-f]+ <[^>]+> bf30      	wfi
  0[0-9a-f]+ <[^>]+> bf40      	sev
  0[0-9a-f]+ <[^>]+> 4408      	add	r0, r1
  0[0-9a-f]+ <[^>]+> 46c0      	nop.*
+ 0[0-9a-f]+ <[^>]+> f3bf 8f5f 	dmb	sy
+ 0[0-9a-f]+ <[^>]+> f3bf 8f4f 	dsb	sy
+ 0[0-9a-f]+ <[^>]+> f3bf 8f6f 	isb	sy
Index: testsuite/gas/arm/archv6m.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/archv6m.s,v
retrieving revision 1.1
diff -c -5 -p -r1.1 archv6m.s
*** testsuite/gas/arm/archv6m.s	5 Mar 2008 01:31:26 -0000	1.1
--- testsuite/gas/arm/archv6m.s	2 Mar 2009 00:20:31 -0000
*************** foo:
*** 12,16 ****
--- 12,20 ----
  	wfe
  	wfi
  	sev
  	add r0, r0, r1
  	nop
+ 	dmb
+ 	dsb
+ 	isb
+