MIPS PLT entry

[Fu, Chao-Ying]

Maciej W. Rozycki wrote:
> 
> On Fri, 12 Jun 2009, Fu, Chao-Ying wrote:
> 
> >   From elfxx-mips.c, we have
> > 
> > /* The format of subsequent PLT entries.  */
> > static const bfd_vma mips_exec_plt_entry[] = {
> >   0x3c0f0000,   /* lui $15, %hi(.got.plt entry)                 */
> >   0x01f90000,   /* l[wd] $25, %lo(.got.plt entry)($15)          */
> >   0x25f80000,   /* addiu $24, $15, %lo(.got.plt entry)          */
> >   0x03200008    /* jr $25                                       */
> > };
> > 
> >   Should we reorder the last two instructions to have jr 
> and then addiu?
> 
>  There is a data dependency between the L[WD] instruction and the JR 
> instruction and therefore for MIPS I processors you need an 
> intermediate 
> instruction to fill the load delay slot.  Of course if building for a 
> higher processor (and in particular for LD, where it is 
> guaranteed) you 
> may swap the instructions, but it cannot be unconditional.

  Yes.  But, this design may hurt the performance.  If a CPU fetches
4 instructions per cycle, it will need to fetch again for the 5th instruction next cycle
and execute the 5th instruction in pipeline stages.  And this 5th instruction is just 
an unused instruction.

  Maybe we need to have conditional compilation on this file for MIPS1 CPUs and
all other MIPS processors.  Thanks!

Ex:
#ifdef FOR_MIPS1
...
#else
...
#endif

Regards,
Chao-ying