regarding assembling branch instruction

[Sivaprasad.pv]

Hi Hans-Peter,

I am also looking for assembler level solution.
For reference, Can you please suggest any example port which uses 
assembler level solution.

Thanks,
Siva Prasad

Hans-Peter Nilsson wrote:
> On Thu, 6 Nov 2008, Nick Clifton wrote:
>   
>> Hi Siva,
>>
>>     
>>> Initially our custom processor support only one unconditional branch
>>> instruction 'bra' of 20 bit range (32 bit instruction).
>>> Now we are planned to add 16 bit unconditional branch instruction 'bra' of 8
>>> bit range.
>>> both shares same instruction name 'bra'.But it leading a problem for us.
>>> For example:
>>>
>>> bra Label
>>> nop
>>> nop
>>> ...
>>> Label: nop
>>>
>>> In first pass 'Label'  address is treated as 0 so it is selecting 16 bit
>>> instruction.
>>> In second pass it finds that the 'Label' is out of 8 bit range and fails to
>>> generate appropriate 32bit instruction opcode.
>>>       
>
> Why the reference to passes?  Passes are not that visible in
> gas.  By "the first pass" I presume you mean "already in
> md_assemble", otherwise you should clarify.
>
>   
>> Either a) delay selecting the opcode to use until the second pass or
>> b) always generate the larger (32bit) opcode in the assembler and then in the
>> linker add code to select the shorter opcode if it can be used. (This process
>> is known as "linker relaxation" and quite a few ports do it.  For an example
>> have a look at bfd/elf-m10300.c).
>>     
>
> I wouldn't recommend linker relaxations as long as there are
> other solutions.  If it's ok to decide already in the assembler,
> I'd instead suggest to have a look at the mechanism for
> TC_GENERIC_RELAX_TABLE, which many ports use for this particular
> purpose.
>
> That and much more, is documented in gas/doc/internals.texi.
>
> brgds, H-P
>
>
>