mips64 xlr processor support
Sandip Matte
sandip@rmicorp.com
Sat Jun 7 12:02:00 GMT 2008
Hello binutils maintainers,
Can somebody please take a look at the xlr processor patch and
let me know the comments.
Thanks,
Sandip
Sandip Matte wrote:
> Hello,
>
> This patch adds support for RMI Corp's mips64 xlr processor.
>
> Thanks,
> Sandip
>
>
> ------------------------------------------------------------------------
>
> 2008-05-27 Sandip Matte <sandip@rmicorp.com>
>
> * bfd/aoutx.h: bfd for xlr mips64 processor.
>
> * bfd/archures.c: define xlr processor.
>
> * bfd/bfd-in2.h: define xlr processor.
>
> * bfd/cpu-mips.c: Add xlr to arch_info_struct.
>
> * doc/archures.texi: define xlr processor.
>
> * bfd/elfxx-mips.c: add xlr bfd in mips_mach_extensions and related
> related places.
>
> * binutils/readelf.c: Define machine flag for xlr processor.
>
> * gas/config/tc-mips.c: Add xlr in mips_cpu_info_table.
> Add new xlr machine instructions: msgld, msgsend, msgwait
>
> * gas/doc/c-mips.texi: Add xlr architecture.
>
> * gas/testsuite/gas/mips/mips.exp: Create mips arch xlr and run dump
> test.
>
> * include/elf/mips.h: Assign a value to machine define for xlr.
>
> * include/opcode/mips.h: Add INSN_XLR flag for xlr instructions.
> Decimal define CPU_XLR is added. Add msg instructions in the macro
> expansion list.
>
> * opcodes/mips-dis.c: Define xlr cop0 regs. Add xlr in
> mips_arch_choices.
>
> * opcodes/mips-opc.c: Add instructions daddwc, ldaddw, ldaddwu, ldaddd,
> mfcr, msgsnd, msgld, msgwait, mtcr, swapw, swapwu, swapd to xlr arch.
>
> * gas/testsuite/gas/mips/xlr-ext.d: Add new file for xlr arch.
>
> * gas/testsuite/gas/mips/xlr-ext.s: new source file to test xlr
> assembler instructions.
>
>
> ------------------------------------------------------------------------
>
> diff -Naur binutils-2.18.orig/bfd/aoutx.h binutils-2.18/bfd/aoutx.h
> --- binutils-2.18.orig/bfd/aoutx.h 2008-05-27 15:04:04.002684000 +0530
> +++ binutils-2.18/bfd/aoutx.h 2008-05-27 15:25:58.000414000 +0530
> @@ -793,6 +793,7 @@
> case bfd_mach_mipsisa64:
> case bfd_mach_mipsisa64r2:
> case bfd_mach_mips_sb1:
> + case bfd_mach_mips_xlr:
> /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
> arch_flags = M_MIPS2;
> break;
> diff -Naur binutils-2.18.orig/bfd/archures.c binutils-2.18/bfd/archures.c
> --- binutils-2.18.orig/bfd/archures.c 2008-05-27 15:04:04.002777000 +0530
> +++ binutils-2.18/bfd/archures.c 2008-05-27 15:25:58.000492000 +0530
> @@ -167,6 +167,7 @@
> .#define bfd_mach_mips16 16
> .#define bfd_mach_mips5 5
> .#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
> +.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
> .#define bfd_mach_mipsisa32 32
> .#define bfd_mach_mipsisa32r2 33
> .#define bfd_mach_mipsisa64 64
> diff -Naur binutils-2.18.orig/bfd/bfd-in2.h binutils-2.18/bfd/bfd-in2.h
> --- binutils-2.18.orig/bfd/bfd-in2.h 2008-05-27 15:04:04.002843000 +0530
> +++ binutils-2.18/bfd/bfd-in2.h 2008-05-27 15:25:58.000539000 +0530
> @@ -1838,6 +1838,7 @@
> #define bfd_mach_mips16 16
> #define bfd_mach_mips5 5
> #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
> +#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
> #define bfd_mach_mipsisa32 32
> #define bfd_mach_mipsisa32r2 33
> #define bfd_mach_mipsisa64 64
> diff -Naur binutils-2.18.orig/bfd/cpu-mips.c binutils-2.18/bfd/cpu-mips.c
> --- binutils-2.18.orig/bfd/cpu-mips.c 2008-05-27 15:04:05.001200000 +0530
> +++ binutils-2.18/bfd/cpu-mips.c 2008-05-27 15:25:58.000718000 +0530
> @@ -87,6 +87,7 @@
> I_mipsisa64,
> I_mipsisa64r2,
> I_sb1,
> + I_xlr,
> };
>
> #define NN(index) (&arch_info_struct[(index) + 1])
> @@ -119,7 +120,8 @@
> N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
> N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
> N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
> - N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
> + N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
> + N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0),
> };
>
> /* The default architecture is mips:3000, but with a machine number of
> diff -Naur binutils-2.18.orig/bfd/doc/archures.texi binutils-2.18/bfd/doc/archures.texi
> --- binutils-2.18.orig/bfd/doc/archures.texi 2008-05-27 15:04:04.000144000 +0530
> +++ binutils-2.18/bfd/doc/archures.texi 2008-05-27 15:25:58.000889000 +0530
> @@ -132,6 +132,7 @@
> #define bfd_mach_mips16 16
> #define bfd_mach_mips5 5
> #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
> +#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
> #define bfd_mach_mipsisa32 32
> #define bfd_mach_mipsisa32r2 33
> #define bfd_mach_mipsisa64 64
> diff -Naur binutils-2.18.orig/bfd/elfxx-mips.c binutils-2.18/bfd/elfxx-mips.c
> --- binutils-2.18.orig/bfd/elfxx-mips.c 2008-05-27 15:04:09.000526000 +0530
> +++ binutils-2.18/bfd/elfxx-mips.c 2008-05-27 15:25:58.001064000 +0530
> @@ -5013,6 +5013,9 @@
> case E_MIPS_MACH_SB1:
> return bfd_mach_mips_sb1;
>
> + case E_MIPS_MACH_XLR:
> + return bfd_mach_mips_xlr;
> +
> default:
> switch (flags & EF_MIPS_ARCH)
> {
> @@ -9177,6 +9180,10 @@
> val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
> break;
>
> + case bfd_mach_mips_xlr:
> + val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
> + break;
> +
> case bfd_mach_mipsisa32:
> val = E_MIPS_ARCH_32;
> break;
> @@ -10908,6 +10915,7 @@
> /* MIPS64 extensions. */
> { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
> { bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
> + { bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
>
> /* MIPS V extensions. */
> { bfd_mach_mipsisa64, bfd_mach_mips5 },
> diff -Naur binutils-2.18.orig/binutils/readelf.c binutils-2.18/binutils/readelf.c
> --- binutils-2.18.orig/binutils/readelf.c 2008-05-27 15:06:01.000062000 +0530
> +++ binutils-2.18/binutils/readelf.c 2008-05-27 15:25:58.001157000 +0530
> @@ -2170,6 +2170,7 @@
> case E_MIPS_MACH_5400: strcat (buf, ", 5400"); break;
> case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
> case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break;
> + case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
> case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
> case 0:
> /* We simply ignore the field in this case to avoid confusion:
> diff -Naur binutils-2.18.orig/gas/config/tc-mips.c binutils-2.18/gas/config/tc-mips.c
> --- binutils-2.18.orig/gas/config/tc-mips.c 2008-05-27 15:04:12.002034000 +0530
> +++ binutils-2.18/gas/config/tc-mips.c 2008-05-27 15:25:58.001357000 +0530
> @@ -442,6 +442,7 @@
> || mips_opts.arch == CPU_R12000 \
> || mips_opts.arch == CPU_RM7000 \
> || mips_opts.arch == CPU_VR5500 \
> + || mips_opts.arch == CPU_XLR \
> )
>
> /* Whether the processor uses hardware interlocks to protect reads
> @@ -466,6 +467,7 @@
> && mips_opts.isa != ISA_MIPS2 \
> && mips_opts.isa != ISA_MIPS3) \
> || mips_opts.arch == CPU_R4300 \
> + || mips_opts.arch == CPU_XLR \
> )
>
> /* Whether the processor uses hardware interlocks to protect reads
> @@ -5866,6 +5868,39 @@
> macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
> break;
>
> + case M_MSGSND: {
> + unsigned long temp = (treg << 16) | (0x01);
> + /*printf("[%s]: treg = %d, temp = %lx\n", __FUNCTION__, treg, temp);*/
> + macro_build((expressionS *)NULL, "c2", "C", temp);
> + }
> + /* AT is not used, just return */
> + return;
> +
> + case M_MSGLD: {
> + unsigned long temp = (0x02);
> + macro_build((expressionS *)NULL, "c2", "C", temp);
> + }
> + /* AT is not used, just return */
> + return;
> + case M_MSGLD_T: {
> + unsigned long temp = (treg << 16) | (0x02);
> + macro_build((expressionS *)NULL, "c2", "C", temp);
> + }
> + /* AT is not used, just return */
> + return;
> +
> + case M_MSGWAIT:
> + macro_build((expressionS *)NULL, "c2", "C", 3);
> + /* AT is not used, just return */
> + return;
> +
> + case M_MSGWAIT_T: {
> + unsigned long temp = (treg << 16) | 0x03;
> + macro_build((expressionS *)NULL, "c2", "C", temp);
> + }
> + /* AT is not used, just return */
> + return;
> +
> case M_J_A:
> /* The j instruction may not be used in PIC code, since it
> requires an absolute address. We convert it to a b
> @@ -14844,6 +14879,9 @@
> { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
> ISA_MIPS64, CPU_SB1 },
>
> + /* RMI Xlr */
> + { "xlr", 0, ISA_MIPS64, CPU_XLR },
> +
> /* End marker */
> { NULL, 0, 0, 0 }
> };
> diff -Naur binutils-2.18.orig/gas/doc/c-mips.texi binutils-2.18/gas/doc/c-mips.texi
> --- binutils-2.18.orig/gas/doc/c-mips.texi 2008-05-27 15:04:15.000641000 +0530
> +++ binutils-2.18/gas/doc/c-mips.texi 2008-05-27 15:25:58.001418000 +0530
> @@ -270,7 +270,8 @@
> 20kc,
> 25kf,
> sb1,
> -sb1a
> +sb1a,
> +xlr
> @end quotation
>
> For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
> diff -Naur binutils-2.18.orig/gas/testsuite/gas/mips/mips.exp binutils-2.18/gas/testsuite/gas/mips/mips.exp
> --- binutils-2.18.orig/gas/testsuite/gas/mips/mips.exp 2008-05-27 15:04:39.001111000 +0530
> +++ binutils-2.18/gas/testsuite/gas/mips/mips.exp 2008-05-27 15:25:58.001468000 +0530
> @@ -361,6 +361,8 @@
> mips_arch_create sb1 64 mips64 { mips3d } \
> { -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
> { mipsisa64sb1-*-* mipsisa64sb1el-*-* }
> +mips_arch_create xlr 64 mips64 {} \
> + { -march=xlr -mtune=xlr } { -mmips:xlr }
>
> #
> # And now begin the actual tests! VxWorks uses RELA rather than REL
> @@ -564,6 +566,7 @@
> run_dump_test "mips64-mdmx"
> run_dump_test "sb1-ext-mdmx"
> run_dump_test "sb1-ext-ps"
> + run_dump_test "xlr-ext"
> }
>
> run_dump_test "relax"
> diff -Naur binutils-2.18.orig/gas/testsuite/gas/mips/xlr-ext.d binutils-2.18/gas/testsuite/gas/mips/xlr-ext.d
> --- binutils-2.18.orig/gas/testsuite/gas/mips/xlr-ext.d 1970-01-01 05:30:00.000000000 +0530
> +++ binutils-2.18/gas/testsuite/gas/mips/xlr-ext.d 2008-05-27 15:25:58.001681000 +0530
> @@ -0,0 +1,20 @@
> +#objdump: -dr --prefix-addresses --show-raw-insn -mmips:xlr
> +#name: XLRs native MIPS64 extensions
> +#as: -march=xlr
> +
> +.*: +file format .*mips.*
> +
> +Disassembly of section .text:
> +0+0000 <[^>]*> 3c000000 lui zero,0x0
> +0+0004 <[^>]*> 8c010001 lw at,1\(zero\)
> +0+0008 <[^>]*> 8c020002 lw v0,2\(zero\)
> +0+000c <[^>]*> 70221838 daddwc v1,at,v0
> +0+0010 <[^>]*> 70230010 ldaddw v1,at
> +0+0014 <[^>]*> 70230011 ldaddwu v1,at
> +0+0018 <[^>]*> 70230012 ldaddd v1,at
> +0+001c <[^>]*> 70230014 swapw v1,at
> +0+0020 <[^>]*> 70230015 swapwu v1,at
> +0+0024 <[^>]*> 4a000003 c2 0x3
> +0+0028 <[^>]*> 4a000002 c2 0x2
> +0+002c <[^>]*> 4a000001 c2 0x1
> + \.\.\.
> diff -Naur binutils-2.18.orig/gas/testsuite/gas/mips/xlr-ext.s binutils-2.18/gas/testsuite/gas/mips/xlr-ext.s
> --- binutils-2.18.orig/gas/testsuite/gas/mips/xlr-ext.s 1970-01-01 05:30:00.000000000 +0530
> +++ binutils-2.18/gas/testsuite/gas/mips/xlr-ext.s 2008-05-27 15:25:58.001689000 +0530
> @@ -0,0 +1,27 @@
> +# Source file used to test XLR's assembler instructions
> +
> + .set noreorder
> + .set noat
> +
> + .globl text_label .text
> +text_label:
> +
> + lui $0, 0x00
> + lw $1, 0x01
> + lw $2, 0x02
> +
> + daddwc $3, $1, $2
> +
> + ldaddw $3, $1
> + ldaddwu $3, $1
> + ldaddd $3, $1
> +
> + swapw $3, $1
> + swapwu $3, $1
> +
> + msgwait
> + msgld $0
> + msgsnd $0
> +
> +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
> + .space 8
> diff -Naur binutils-2.18.orig/include/elf/mips.h binutils-2.18/include/elf/mips.h
> --- binutils-2.18.orig/include/elf/mips.h 2008-05-27 15:04:58.000419000 +0530
> +++ binutils-2.18/include/elf/mips.h 2008-05-27 15:25:58.001517000 +0530
> @@ -213,6 +213,7 @@
> #define E_MIPS_MACH_4120 0x00870000
> #define E_MIPS_MACH_4111 0x00880000
> #define E_MIPS_MACH_SB1 0x008a0000
> +#define E_MIPS_MACH_XLR 0x008c0000
> #define E_MIPS_MACH_5400 0x00910000
> #define E_MIPS_MACH_5500 0x00980000
> #define E_MIPS_MACH_9000 0x00990000
> diff -Naur binutils-2.18.orig/include/opcode/mips.h binutils-2.18/include/opcode/mips.h
> --- binutils-2.18.orig/include/opcode/mips.h 2008-05-27 15:04:59.000286000 +0530
> +++ binutils-2.18/include/opcode/mips.h 2008-05-27 15:45:52.000050000 +0530
> @@ -520,6 +520,8 @@
> #define INSN_5400 0x01000000
> /* NEC VR5500 instruction. */
> #define INSN_5500 0x02000000
> +/* RMI Xlr instruction */
> +#define INSN_XLR 0x04000000
>
> /* MDMX ASE */
> #define INSN_MDMX 0x04000000
> @@ -576,6 +578,7 @@
> #define CPU_MIPS64 64
> #define CPU_MIPS64R2 65
> #define CPU_SB1 12310201 /* octal 'SB', 01. */
> +#define CPU_XLR 887682 /* decimal 'XLR' */
>
> /* Test for membership in an ISA including chip specific ISAs. INSN
> is pointer to an element of the opcode table; ISA is the specified
> @@ -597,6 +600,7 @@
> || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
> || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
> || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
> + || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
> || 0) /* Please keep this term for easier source merging. */
>
> /* This is a list of macro expanded instructions.
> @@ -730,6 +734,11 @@
> M_LWR_AB,
> M_LWU_AB,
> M_MOVE,
> + M_MSGSND,
> + M_MSGLD,
> + M_MSGLD_T,
> + M_MSGWAIT,
> + M_MSGWAIT_T,
> M_MUL,
> M_MUL_I,
> M_MULO,
> diff -Naur binutils-2.18.orig/opcodes/mips-dis.c binutils-2.18/opcodes/mips-dis.c
> --- binutils-2.18.orig/opcodes/mips-dis.c 2008-05-27 15:05:05.000848000 +0530
> +++ binutils-2.18/opcodes/mips-dis.c 2008-05-27 15:52:18.000047000 +0530
> @@ -295,6 +295,56 @@
> { 29, 3, "c0_datahi_d" },
> };
>
> +/* Xlr cop0 register names */
> +static const char * const mips_cp0_names_xlr[32] = {
> + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
> + "c0_context", "c0_pagemask", "c0_wired", "$7",
> + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
> + "c0_status", "c0_cause", "c0_epc", "c0_prid",
> + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
> + "c0_xcontext", "$21", "$22", "c0_debug",
> + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
> + "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
> +};
> +
> +/* XLR's CP0 Select Registers */
> +
> +static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
> + { 9, 6, "c0_extintreq" },
> + { 9, 7, "c0_extintmask" },
> + { 15, 1, "c0_ebase" },
> + { 16, 1, "c0_config1" },
> + { 16, 2, "c0_config2" },
> + { 16, 3, "c0_config3" },
> + { 16, 7, "c0_procid2" },
> + { 18, 1, "c0_watchlo,1" },
> + { 18, 2, "c0_watchlo,2" },
> + { 18, 3, "c0_watchlo,3" },
> + { 18, 4, "c0_watchlo,4" },
> + { 18, 5, "c0_watchlo,5" },
> + { 18, 6, "c0_watchlo,6" },
> + { 18, 7, "c0_watchlo,7" },
> + { 19, 1, "c0_watchhi,1" },
> + { 19, 2, "c0_watchhi,2" },
> + { 19, 3, "c0_watchhi,3" },
> + { 19, 4, "c0_watchhi,4" },
> + { 19, 5, "c0_watchhi,5" },
> + { 19, 6, "c0_watchhi,6" },
> + { 19, 7, "c0_watchhi,7" },
> + { 25, 1, "c0_perfcnt,1" },
> + { 25, 2, "c0_perfcnt,2" },
> + { 25, 3, "c0_perfcnt,3" },
> + { 25, 4, "c0_perfcnt,4" },
> + { 25, 5, "c0_perfcnt,5" },
> + { 25, 6, "c0_perfcnt,6" },
> + { 25, 7, "c0_perfcnt,7" },
> + { 27, 1, "c0_cacheerr,1" },
> + { 27, 2, "c0_cacheerr,2" },
> + { 27, 3, "c0_cacheerr,3" },
> + { 28, 1, "c0_datalo" },
> + { 29, 1, "c0_datahi" }
> +};
> +
> static const char * const mips_hwr_names_numeric[32] =
> {
> "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
> @@ -426,6 +476,12 @@
> mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
> mips_hwr_names_numeric },
>
> + { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
> + ISA_MIPS64 | INSN_XLR,
> + mips_cp0_names_xlr,
> + mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
> + mips_hwr_names_numeric },
> +
> /* This entry, mips16, is here only for ISA/processor selection; do
> not print its name. */
> { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
> diff -Naur binutils-2.18.orig/opcodes/mips-opc.c binutils-2.18/opcodes/mips-opc.c
> --- binutils-2.18.orig/opcodes/mips-opc.c 2008-05-27 15:05:05.000890000 +0530
> +++ binutils-2.18/opcodes/mips-opc.c 2008-05-27 15:25:58.001644000 +0530
> @@ -113,6 +113,7 @@
> #define N5 (INSN_5400 | INSN_5500)
> #define N54 INSN_5400
> #define N55 INSN_5500
> +#define XLR INSN_XLR
>
> #define G1 (T3 \
> )
> @@ -513,6 +514,7 @@
> {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
> {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
> {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
> +{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,0, XLR },
> {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
> {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
> {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
> @@ -688,6 +690,9 @@
> {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
> {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
> {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
> +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
> +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
> +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
> {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
> {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
> {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
> @@ -816,6 +821,7 @@
> {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
> {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
> {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
> +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR },
> {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
> {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
> {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
> @@ -856,6 +862,11 @@
> {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
> /* move is at the top of the table. */
> {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
> +{"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR },
> +{"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR },
> +{"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR },
> +{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR },
> +{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR },
> {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
> {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
> {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
> @@ -882,6 +893,7 @@
> {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
> {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
> {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
> +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR },
> {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
> {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
> {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
> @@ -1175,6 +1187,9 @@
> {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55},
> {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
> {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
> +{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
> +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
> +{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
> {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
> {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
> {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
--
The bulk of the worldÂ’s knowledge is an imaginary construction. -Helen Keller
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