PATCH: Remove Intel syntax workaround in x86 assembler

H.J. Lu hjl@lucon.org
Mon Jan 7 18:12:00 GMT 2008


X86 assembler has a workaround for Intel syntax due to incompatible
AT&T mnemonic. Since we can now skip AT&T mnemonic at runtime,
I am checking in this patch to remove the workaround.

H.J.
---
gas/

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic.

	* config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic
	only.
	(md_assemble): Remove Intel mode workaround.
	(match_template): Check support for old gcc, AT&T mnemonic
	and Intel Syntax.
	(md_parse_option): Don't set intel_mnemonic to 0 for
	OPTION_MOLD_GCC.

gas/testsuite/

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp,
	fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp.

	* gas/i386/intel.d: Updated.
	* gas/i386/intel.e: Likewise.

opcodes/

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

Index: opcodes/i386-opc.tbl
===================================================================
--- opcodes/i386-opc.tbl	(revision 1184)
+++ opcodes/i386-opc.tbl	(working copy)
@@ -613,37 +613,41 @@ faddp, 2, 0xdec0, None, 2, 0, ShortForm|
 
 // subtract
 fsub, 1, 0xd8e0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
-fsub, 2, 0xd8e0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
+fsub, 2, 0xd8e0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 // alias for fsubp
-fsub, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
-fsub, 2, 0xd8e0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
+fsub, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 }
+fsub, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
+fsub, 2, 0xd8e0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
 fsub, 1, 0xd8, 0x4, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 fisub, 1, 0xde, 0x4, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 
-fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
-fsubp, 1, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
-fsubp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
-fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
-fsubp, 2, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
-fsubp, 1, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
-fsubp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
+fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fsubp, 1, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fsubp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
+fsubp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
+fsubp, 2, 0xdee9, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
+fsubp, 2, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
+fsubp, 1, 0xdee8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
+fsubp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // subtract reverse
 fsubr, 1, 0xd8e8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
-fsubr, 2, 0xd8e8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
+fsubr, 2, 0xd8e8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 // alias for fsubrp
-fsubr, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
-fsubr, 2, 0xd8e8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
+fsubr, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 }
+fsubr, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
+fsubr, 2, 0xd8e8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
 fsubr, 1, 0xd8, 0x5, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 fisubr, 1, 0xde, 0x5, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 
-fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
-fsubrp, 1, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
-fsubrp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
-fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
-fsubrp, 2, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
-fsubrp, 1, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
-fsubrp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
+fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fsubrp, 1, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fsubrp, 0, 0xdee9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
+fsubrp, 2, 0xdee8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
+fsubrp, 2, 0xdee0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
+fsubrp, 2, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
+fsubrp, 1, 0xdee0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
+fsubrp, 0, 0xdee1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
 
 // multiply
 fmul, 2, 0xd8c8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
@@ -660,37 +664,41 @@ fmulp, 2, 0xdec8, None, 2, 0, ShortForm|
 
 // divide
 fdiv, 1, 0xd8f0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
-fdiv, 2, 0xd8f0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
+fdiv, 2, 0xd8f0, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 // alias for fdivp
-fdiv, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
-fdiv, 2, 0xd8f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
+fdiv, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 }
+fdiv, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
+fdiv, 2, 0xd8f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
 fdiv, 1, 0xd8, 0x6, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 fidiv, 1, 0xde, 0x6, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 
-fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
-fdivp, 1, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
-fdivp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
-fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
-fdivp, 2, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
-fdivp, 1, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
-fdivp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic, { 0 }
+fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fdivp, 1, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fdivp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
+fdivp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
+fdivp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
+fdivp, 2, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
+fdivp, 1, 0xdef8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
+fdivp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
 
 // divide reverse
 fdivr, 1, 0xd8f8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
-fdivr, 2, 0xd8f8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg, FloatAcc }
+fdivr, 2, 0xd8f8, None, 2, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 // alias for fdivrp
-fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
-fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR|IntelMnemonic, { FloatReg, FloatAcc }
+fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 }
+fdivr, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
+fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
 fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 
-fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatAcc, FloatReg }
-fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { FloatReg }
-fdivrp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic, { 0 }
-fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
-fdivrp, 2, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatAcc, FloatReg }
-fdivrp, 1, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|IntelMnemonic, { FloatReg }
-fdivrp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IntelMnemonic,	{ 0 }
+fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fdivrp, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
+fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
+fdivrp, 2, 0xdef0, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
+fdivrp, 2, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
+fdivrp, 1, 0xdef0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
+fdivrp, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf,	{ 0 }
 
 f2xm1, 0, 0xd9f0, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 fyl2x, 0, 0xd9f1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
Index: opcodes/i386-gen.c
===================================================================
--- opcodes/i386-gen.c	(revision 1184)
+++ opcodes/i386-gen.c	(working copy)
@@ -297,7 +297,7 @@ static bitfield opcode_modifiers[] =
   BITFIELD (Drexc),
   BITFIELD (OldGcc),
   BITFIELD (ATTMnemonic),
-  BITFIELD (IntelMnemonic),
+  BITFIELD (ATTSyntax),
 };
 
 static bitfield operand_types[] =
Index: opcodes/i386-opc.h
===================================================================
--- opcodes/i386-opc.h	(revision 1184)
+++ opcodes/i386-opc.h	(working copy)
@@ -237,10 +237,10 @@ typedef union i386_cpu_flags
 #define OldGcc			(Drexc + 1)
 /* AT&T mnemonic.  */
 #define ATTMnemonic		(OldGcc + 1)
-/* Intel mnemonic.  */
-#define IntelMnemonic		(ATTMnemonic + 1)
+/* AT&T syntax.  */
+#define ATTSyntax		(ATTMnemonic + 1)
 /* The last bitfield in i386_opcode_modifier.  */
-#define Opcode_Modifier_Max	IntelMnemonic
+#define Opcode_Modifier_Max	ATTSyntax
 
 typedef struct i386_opcode_modifier
 {
@@ -290,7 +290,7 @@ typedef struct i386_opcode_modifier
   unsigned int drexc:1;
   unsigned int oldgcc:1;
   unsigned int attmnemonic:1;
-  unsigned int intelmnemonic:1;
+  unsigned int attsyntax:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */
Index: gas/doc/c-i386.texi
===================================================================
--- gas/doc/c-i386.texi	(revision 1184)
+++ gas/doc/c-i386.texi	(working copy)
@@ -139,8 +139,7 @@ take precedent.
 @cindex @samp{-mnaked-reg} option, x86-64
 @item -mnaked-reg
 This opetion specifies that registers don't require a @samp{%} prefix.
-The @code{.att_mnemonic}, @code{.intel_mnemonic}, @code{.att_syntax} and
-@code{.intel_syntax} directives will take precedent.
+The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
 
 @end table
 
@@ -329,8 +328,6 @@ convention.
 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
 syntax for compatibility with the output of @code{@value{GCC}}.
-Either of these directives may have an optional argument, @code{prefix},
-or @code{noprefix} specifying whether registers require a @samp{%} prefix.
 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
 @samp{fsubr} and @samp{fsubrp},  are implemented in AT&T System V/386
Index: gas/testsuite/gas/i386/intel.d
===================================================================
--- gas/testsuite/gas/i386/intel.d	(revision 1184)
+++ gas/testsuite/gas/i386/intel.d	(working copy)
@@ -630,4 +630,62 @@ Disassembly of section .text:
  a8b:	b3 47 [ 	]*mov    \$0x47,%bl
  a8d:	0f ad d0 [ 	]*shrd   %cl,%edx,%eax
  a90:	0f a5 d0 [ 	]*shld   %cl,%edx,%eax
-[ 	]*...
+[ 	]*[a-f0-9]+:	de c1                	faddp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	d8 c3                	fadd   %st\(3\),%st
+[ 	]*[a-f0-9]+:	d8 c3                	fadd   %st\(3\),%st
+[ 	]*[a-f0-9]+:	dc c3                	fadd   %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 03                	fadds  \(%ebx\)
+[ 	]*[a-f0-9]+:	dc 03                	faddl  \(%ebx\)
+[ 	]*[a-f0-9]+:	de c1                	faddp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de c3                	faddp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de c3                	faddp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de f9                	fdivrp %st,%st\(1\)
+[ 	]*[a-f0-9]+:	d8 f3                	fdiv   %st\(3\),%st
+[ 	]*[a-f0-9]+:	d8 f3                	fdiv   %st\(3\),%st
+[ 	]*[a-f0-9]+:	dc fb                	fdivr  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 33                	fdivs  \(%ebx\)
+[ 	]*[a-f0-9]+:	dc 33                	fdivl  \(%ebx\)
+[ 	]*[a-f0-9]+:	de f9                	fdivrp %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de fb                	fdivrp %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de fb                	fdivrp %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de fb                	fdivrp %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de f1                	fdivp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	d8 fb                	fdivr  %st\(3\),%st
+[ 	]*[a-f0-9]+:	d8 fb                	fdivr  %st\(3\),%st
+[ 	]*[a-f0-9]+:	dc f3                	fdiv   %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 3b                	fdivrs \(%ebx\)
+[ 	]*[a-f0-9]+:	dc 3b                	fdivrl \(%ebx\)
+[ 	]*[a-f0-9]+:	de f1                	fdivp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de f3                	fdivp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de f3                	fdivp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de f3                	fdivp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de c9                	fmulp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	d8 cb                	fmul   %st\(3\),%st
+[ 	]*[a-f0-9]+:	d8 cb                	fmul   %st\(3\),%st
+[ 	]*[a-f0-9]+:	dc cb                	fmul   %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 0b                	fmuls  \(%ebx\)
+[ 	]*[a-f0-9]+:	dc 0b                	fmull  \(%ebx\)
+[ 	]*[a-f0-9]+:	de c9                	fmulp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de cb                	fmulp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de cb                	fmulp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de e9                	fsubrp %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de e1                	fsubp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	d8 e3                	fsub   %st\(3\),%st
+[ 	]*[a-f0-9]+:	d8 e3                	fsub   %st\(3\),%st
+[ 	]*[a-f0-9]+:	dc eb                	fsubr  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 23                	fsubs  \(%ebx\)
+[ 	]*[a-f0-9]+:	dc 23                	fsubl  \(%ebx\)
+[ 	]*[a-f0-9]+:	de e9                	fsubrp %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de eb                	fsubrp %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de eb                	fsubrp %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de eb                	fsubrp %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 eb                	fsubr  %st\(3\),%st
+[ 	]*[a-f0-9]+:	d8 eb                	fsubr  %st\(3\),%st
+[ 	]*[a-f0-9]+:	dc e3                	fsub   %st,%st\(3\)
+[ 	]*[a-f0-9]+:	d8 2b                	fsubrs \(%ebx\)
+[ 	]*[a-f0-9]+:	dc 2b                	fsubrl \(%ebx\)
+[ 	]*[a-f0-9]+:	de e1                	fsubp  %st,%st\(1\)
+[ 	]*[a-f0-9]+:	de e3                	fsubp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de e3                	fsubp  %st,%st\(3\)
+[ 	]*[a-f0-9]+:	de e3                	fsubp  %st,%st\(3\)
+#pass
Index: gas/testsuite/gas/i386/intel.e
===================================================================
--- gas/testsuite/gas/i386/intel.e	(revision 1184)
+++ gas/testsuite/gas/i386/intel.e	(working copy)
@@ -1,7 +1,17 @@
 .*: Assembler messages:
-.*:154: Warning: Treating .\[0x90909090\]. as memory reference
-.*:155: Warning: Treating .\[0x90909090\]. as memory reference
-.*:156: Warning: Treating .\[0x90909090\]. as memory reference
-.*:157: Warning: Treating .\[0x90909090\]. as memory reference
-.*:492: Warning: Treating .\[0x90909090\]. as memory reference
-.*:493: Warning: Treating .\[0x90909090\]. as memory reference
+.*:154: Warning: Treating `\[0x90909090\]' as memory reference
+.*:155: Warning: Treating `\[0x90909090\]' as memory reference
+.*:156: Warning: Treating `\[0x90909090\]' as memory reference
+.*:157: Warning: Treating `\[0x90909090\]' as memory reference
+.*:492: Warning: Treating `\[0x90909090\]' as memory reference
+.*:493: Warning: Treating `\[0x90909090\]' as memory reference
+.*:631: Warning: translating to `faddp'
+.*:640: Warning: translating to `fdivp'
+.*:649: Warning: translating to `fdivp st,st\(3\)'
+.*:650: Warning: translating to `fdivrp'
+.*:659: Warning: translating to `fdivrp st,st\(3\)'
+.*:660: Warning: translating to `fmulp'
+.*:669: Warning: translating to `fsubp'
+.*:670: Warning: translating to `fsubrp'
+.*:678: Warning: translating to `fsubp st,st\(3\)'
+.*:688: Warning: translating to `fsubrp st,st\(3\)'
Index: gas/testsuite/gas/i386/intel.s
===================================================================
--- gas/testsuite/gas/i386/intel.s	(revision 1184)
+++ gas/testsuite/gas/i386/intel.s	(working copy)
@@ -628,4 +628,61 @@ rot5:
  shrd   eax, edx, cl
  shld   eax, edx, cl
 
- .p2align 4,0
+fadd
+fadd	st(3)
+fadd	st,st(3)
+fadd	st(3),st
+fadd   DWORD PTR [ebx]
+fadd   QWORD PTR [ebx]
+faddp
+faddp	st(3)
+faddp	st(3),st
+fdiv
+fdiv   st(3)
+fdiv   st,st(3)
+fdiv   st(3),st
+fdiv   DWORD PTR [ebx]
+fdiv   QWORD PTR [ebx]
+fdivp
+fdivp  st(3)
+fdivp  st(3),st
+fdivp  st,st(3)
+fdivr
+fdivr  st(3)
+fdivr  st,st(3)
+fdivr  st(3),st
+fdivr  DWORD PTR [ebx]
+fdivr  QWORD PTR [ebx]
+fdivrp
+fdivrp st(3)
+fdivrp st(3),st
+fdivrp st,st(3)
+fmul
+fmul	st(3)
+fmul	st,st(3)
+fmul	st(3),st
+fmul   DWORD PTR [ebx]
+fmul   QWORD PTR [ebx]
+fmulp
+fmulp	st(3)
+fmulp	st(3),st
+fsub
+fsubr
+fsub   st(3)
+fsub   st,st(3)
+fsub   st(3),st
+fsub   DWORD PTR [ebx]
+fsub   QWORD PTR [ebx]
+fsubp
+fsubp  st(3)
+fsubp  st,st(3)
+fsubp  st(3),st
+fsubr  st(3)
+fsubr  st,st(3)
+fsubr  st(3),st
+fsubr  DWORD PTR [ebx]
+fsubr  QWORD PTR [ebx]
+fsubrp
+fsubrp st(3)
+fsubrp st(3),st
+fsubrp st,st(3)
Index: gas/config/tc-i386.c
===================================================================
--- gas/config/tc-i386.c	(revision 1184)
+++ gas/config/tc-i386.c	(working copy)
@@ -1495,37 +1495,7 @@ set_intel_syntax (int syntax_flag)
 static void
 set_intel_mnemonic (int mnemonic_flag)
 {
-  /* Find out if register prefixing is specified.  */
-  int ask_naked_reg = 0;
-
-  SKIP_WHITESPACE ();
-  if (!is_end_of_line[(unsigned char) *input_line_pointer])
-    {
-      char *string = input_line_pointer;
-      int e = get_symbol_end ();
-
-      if (strcmp (string, "prefix") == 0)
-	ask_naked_reg = 1;
-      else if (strcmp (string, "noprefix") == 0)
-	ask_naked_reg = -1;
-      else
-	as_bad (_("bad argument to syntax directive."));
-      *input_line_pointer = e;
-    }
-  demand_empty_rest_of_line ();
-
-  /* intel_mnemonic implies intel_syntax.  */
-  intel_mnemonic = intel_syntax = mnemonic_flag;
-
-  if (ask_naked_reg == 0)
-    allow_naked_reg = (intel_mnemonic
-		       && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
-  else
-    allow_naked_reg = (ask_naked_reg < 0);
-
-  identifier_chars['%'] = intel_mnemonic && allow_naked_reg ? '%' : 0;
-  identifier_chars['$'] = intel_mnemonic ? '$' : 0;
-  register_prefix = allow_naked_reg ? "" : "%";
+  intel_mnemonic = mnemonic_flag;
 }
 
 static void
@@ -2205,12 +2175,6 @@ md_assemble (line)
 
   if (intel_syntax)
     {
-      /* Undo AT&T Mnemonic brokenness when in Intel mode.  See
-	 i386-opc.tbl.  */
-      if (!intel_mnemonic
-	  && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
-	i.tm.base_opcode ^= Opcode_FloatR;
-
       /* Zap movzx and movsx suffix.  The suffix may have been set from
 	 "word ptr" or "byte ptr" on the source operand, but we'll use
 	 the suffix later to choose the destination register.  */
@@ -3035,15 +2999,16 @@ match_template (void)
       if (i.operands != t->operands)
 	continue;
 
-      /* Check AT&T mnemonic and old gcc support. */
-      if (t->opcode_modifier.attmnemonic
-	  && (intel_mnemonic
-	      || (!old_gcc
-		  && t->opcode_modifier.oldgcc)))
+      /* Check old gcc support. */
+      if (!old_gcc && t->opcode_modifier.oldgcc)
+	continue;
+
+      /* Check AT&T mnemonic.   */
+      if (intel_mnemonic && t->opcode_modifier.attmnemonic)
 	continue;
 
-      /* Check Intel mnemonic. */
-      if (!intel_mnemonic && t->opcode_modifier.intelmnemonic)
+      /* Check Intel syntax.   */
+      if (intel_syntax && t->opcode_modifier.attsyntax)
 	continue;
 
       /* Check the suffix, except for some instructions in intel mode.  */
@@ -7134,7 +7099,6 @@ md_parse_option (int c, char *arg)
 
     case OPTION_MOLD_GCC:
       old_gcc = 1;
-      intel_mnemonic = 0;
       break;
 
     default:



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