Common SSE4.1/SSE5 insns broken

H.J. Lu hjl@lucon.org
Fri Jan 4 18:09:00 GMT 2008


On Fri, Dec 28, 2007 at 07:45:16AM -0800, H.J. Lu wrote:
> On Fri, Dec 28, 2007 at 10:10:34AM +0100, Jakub Jelinek wrote:
> > Hi!
> > 
> > Doesn't CpuSSE4_1|CpuSSE5 mean it requires SSE4.1 AND SSE5 rather than
> > SSE4.1 OR SSE5?
> > 
> > Say e.g.:
> > 
> > .arch generic64
> > .arch .sse5
> > ptest           %xmm1,%xmm0
> > frczss          %xmm2, %xmm1
> > 
> > fails to assemble with
> > Warning: `ptest' is not supported on `generic64.sse5'
> > Error: suffix or operands invalid for `ptest'
> > 
> > and likewise for .arch .sse4.1.  Works if both .sse5 and .sse4.1
> > are present.  Do we need yet another bit for the common
> > SSE4.1 / SSE5 instructions, which .sse4.1, .sse5 would
> > both set (and be set in unknown too)?
> > 
> 
> I am checking in this patch to fix it.
> 

Have CpuSSE4_1|CpuSSE5 mean it requires SSE4.1 OR SSE5 makes
more senses than requires SSE4.1 AND SSE5. Also warning in

Warning: `ptest' is not supported on `generic64.sse5'
Error: suffix or operands invalid for `ptest'

should be error. Here is a patch to implement it. I also removed
Cpu686 from Cpu686|CpuPadLock.

Are there any objections?


H.J.
----
gas/

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
	(cpu_flags_not): Likewise.
	(cpu_flags_match): Updated to check 64bit and arch.
	(set_code_flag): Remove cpu_arch_flags_not.
	(set_16bit_gcc_code_flag): Likewise.
	(set_cpu_arch): Likewise.
	(md_begin): Likewise.
	(parse_insn): Call cpu_flags_match to check 64bit and arch.
	(match_template): Likewise.

gas/testsuite/

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-9.d: New file.
	* gas/i386/arch-9.s: Likewise.

	* gas/i386/i386.exp: Run arch-9.

opcodes/

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

--- binutils/gas/config/tc-i386.c.arch	2008-01-03 12:09:48.000000000 -0800
+++ binutils/gas/config/tc-i386.c	2008-01-03 14:02:45.000000000 -0800
@@ -318,9 +318,6 @@ static const char *cpu_sub_arch_name = N
 /* CPU feature flags.  */
 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
 
-/* Bitwise NOT of cpu_arch_flags.  */
-static i386_cpu_flags cpu_arch_flags_not;
-
 /* If we have selected a cpu we are generating instructions for.  */
 static int cpu_arch_tune_set = 0;
 
@@ -967,29 +964,6 @@ cpu_flags_check_cpu64 (i386_cpu_flags f)
 }
 
 static INLINE i386_cpu_flags
-cpu_flags_not (i386_cpu_flags x)
-{
-  switch (ARRAY_SIZE (x.array))
-    {
-    case 3:
-      x.array [2] = ~x.array [2];
-    case 2:
-      x.array [1] = ~x.array [1];
-    case 1:
-      x.array [0] = ~x.array [0];
-      break;
-    default:
-      abort ();
-    }
-
-#ifdef CpuUnused
-  x.bitfield.unused = 0;
-#endif
-
-  return x;
-}
-
-static INLINE i386_cpu_flags
 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
 {
   switch (ARRAY_SIZE (x.array))
@@ -1025,19 +999,29 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu
   return x;
 }
 
+/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
+   1 if compatible with arch, 0 if there is no match.  */
+
 static int
 cpu_flags_match (i386_cpu_flags x)
 {
-  i386_cpu_flags not = cpu_arch_flags_not;
-
-  not.bitfield.cpu64 = 1;
-  not.bitfield.cpuno64 = 1;
+  int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
 
   x.bitfield.cpu64 = 0;
   x.bitfield.cpuno64 = 0;
 
-  not = cpu_flags_and (x, not);
-  return UINTS_ALL_ZERO (not);
+  if (UINTS_ALL_ZERO (x))
+    overlap |= 1;
+  else
+    {
+      i386_cpu_flags cpu = cpu_arch_flags;
+
+      cpu.bitfield.cpu64 = 0;
+      cpu.bitfield.cpuno64 = 0;
+      cpu = cpu_flags_and (x, cpu);
+      overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
+    }
+  return overlap;
 }
 
 static INLINE i386_operand_type
@@ -1445,15 +1429,11 @@ set_code_flag (int value)
     {
       cpu_arch_flags.bitfield.cpu64 = 1;
       cpu_arch_flags.bitfield.cpuno64 = 0;
-      cpu_arch_flags_not.bitfield.cpu64 = 0;
-      cpu_arch_flags_not.bitfield.cpuno64 = 1;
     }
   else
     {
       cpu_arch_flags.bitfield.cpu64 = 0;
       cpu_arch_flags.bitfield.cpuno64 = 1;
-      cpu_arch_flags_not.bitfield.cpu64 = 1;
-      cpu_arch_flags_not.bitfield.cpuno64 = 0;
     }
   if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
     {
@@ -1474,8 +1454,6 @@ set_16bit_gcc_code_flag (int new_code_fl
     abort ();
   cpu_arch_flags.bitfield.cpu64 = 0;
   cpu_arch_flags.bitfield.cpuno64 = 1;
-  cpu_arch_flags_not.bitfield.cpu64 = 1;
-  cpu_arch_flags_not.bitfield.cpuno64 = 0;
   stackop_size = LONG_MNEM_SUFFIX;
 }
 
@@ -1587,7 +1565,6 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
 		      cpu_arch_flags.bitfield.cpu64 = 0;
 		      cpu_arch_flags.bitfield.cpuno64 = 1;
 		    }
-		  cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
 		  cpu_arch_isa = cpu_arch[i].type;
 		  cpu_arch_isa_flags = cpu_arch[i].flags;
 		  if (!cpu_arch_tune_set)
@@ -1604,7 +1581,6 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
 		{
 		  cpu_sub_arch_name = cpu_arch[i].name;
 		  cpu_arch_flags = flags;
-		  cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
 		}
 	      *input_line_pointer = e;
 	      demand_empty_rest_of_line ();
@@ -1655,8 +1631,6 @@ md_begin ()
 {
   const char *hash_err;
 
-  cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
-
   /* Initialize op_hash hash table.  */
   op_hash = hash_new ();
 
@@ -2582,11 +2556,11 @@ parse_insn (char *line, char *mnemonic)
   supported = 0;
   for (t = current_templates->start; t < current_templates->end; ++t)
     {
-      if (cpu_flags_match (t->cpu_flags))
-	supported |= 1;
-      if (cpu_flags_check_cpu64 (t->cpu_flags))
-	supported |= 2;
+      supported |= cpu_flags_match (t->cpu_flags);
+      if (supported == 3)
+	goto skip;
     }
+
   if (!(supported & 2))
     {
       as_bad (flag_code == CODE_64BIT
@@ -2597,12 +2571,14 @@ parse_insn (char *line, char *mnemonic)
     }
   if (!(supported & 1))
     {
-      as_warn (_("`%s' is not supported on `%s%s'"),
-	       current_templates->start->name,
-	       cpu_arch_name,
-	       cpu_sub_arch_name ? cpu_sub_arch_name : "");
+      as_bad (_("`%s' is not supported on `%s%s'"),
+	      current_templates->start->name, cpu_arch_name,
+	      cpu_sub_arch_name ? cpu_sub_arch_name : "");
+      return NULL;
     }
-  else if (!cpu_arch_flags.bitfield.cpui386
+
+skip:
+  if (!cpu_arch_flags.bitfield.cpui386
 	   && (flag_code != CODE_16BIT))
     {
       as_warn (_("use .code16 to ensure correct addressing mode"));
@@ -3025,7 +3001,7 @@ match_template (void)
   i386_operand_type operand_types [MAX_OPERANDS];
   int addr_prefix_disp;
   unsigned int j;
-  i386_cpu_flags overlap;
+  unsigned int found_cpu_match;
 
 #if MAX_OPERANDS != 4
 # error "MAX_OPERANDS must be 4."
@@ -3112,10 +3088,10 @@ match_template (void)
       /* Do not verify operands when there are none.  */
       else 
 	{
-	  overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
+	  found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
 	  if (!t->operands)
 	    {
-	      if (!UINTS_ALL_ZERO (overlap))
+	      if (!found_cpu_match)
 		continue;
 	      /* We've found a match; break out of loop.  */
 	      break;
@@ -3279,7 +3255,7 @@ match_template (void)
 	  /* Found either forward/reverse 2, 3 or 4 operand match here:
 	     slip through to break.  */
 	}
-      if (!UINTS_ALL_ZERO (overlap))
+      if (!found_cpu_match)
 	{
 	  found_reverse_match = 0;
 	  continue;
--- binutils/gas/testsuite/gas/i386/arch-9.d.arch	2008-01-03 13:43:13.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-9.d	2008-01-03 13:47:43.000000000 -0800
@@ -0,0 +1,10 @@
+#objdump: -dw
+#name: i386 arch 9
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+#pass
--- binutils/gas/testsuite/gas/i386/i386.exp.arch	2008-01-03 10:57:32.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/i386.exp	2008-01-03 13:42:54.000000000 -0800
@@ -106,6 +106,7 @@ if [expr ([istarget "i*86-*-*"] ||  [ist
     run_dump_test "arch-6"
     run_dump_test "arch-7"
     run_dump_test "arch-8"
+    run_dump_test "arch-9"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
--- binutils/opcodes/i386-gen.c.arch	2008-01-03 12:09:48.000000000 -0800
+++ binutils/opcodes/i386-gen.c	2008-01-03 12:18:01.000000000 -0800
@@ -81,7 +81,7 @@ static initializer cpu_flag_init [] =
   { "CPU_K8_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
   { "CPU_AMDFAM10_FLAGS",
-    "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE4_2_Or_ABM|CpuLM" },
+    "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
   { "CPU_MMX_FLAGS",
     "CpuMMX" },
   { "CPU_SSE_FLAGS",
@@ -93,9 +93,9 @@ static initializer cpu_flag_init [] =
   { "CPU_SSSE3_FLAGS",
     "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" },
   { "CPU_SSE4_1_FLAGS",
-    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_1_Or_5" },
+    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" },
   { "CPU_SSE4_2_FLAGS",
-    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM" },
+    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" },
   { "CPU_3DNOW_FLAGS",
     "CpuMMX|Cpu3dnow" },
   { "CPU_3DNOWA_FLAGS",
@@ -107,9 +107,9 @@ static initializer cpu_flag_init [] =
   { "CPU_SSE4A_FLAGS",
     "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
   { "CPU_ABM_FLAGS",
-    "CpuABM|CpuSSE4_2_Or_ABM" },
+    "CpuABM" },
   { "CPU_SSE5_FLAGS",
-    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM"},
+    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5"},
 };
 
 static initializer operand_type_init [] =
@@ -234,8 +234,6 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuSSE4_2),
   BITFIELD (CpuSSE4a),
   BITFIELD (CpuSSE5),
-  BITFIELD (CpuSSE4_1_Or_5),
-  BITFIELD (CpuSSE4_2_Or_ABM),
   BITFIELD (Cpu3dnow),
   BITFIELD (Cpu3dnowA),
   BITFIELD (CpuPadLock),
--- binutils/opcodes/i386-opc.h.arch	2008-01-03 12:09:48.000000000 -0800
+++ binutils/opcodes/i386-opc.h	2008-01-03 12:20:21.000000000 -0800
@@ -82,12 +82,8 @@
 #define CpuSSE4_2	(CpuSSE4_1 + 1)
 /* SSE5 support required */
 #define CpuSSE5		(CpuSSE4_2 + 1)
-/* SSE4.1 or SSE5 support required */
-#define CpuSSE4_1_Or_5	(CpuSSE5 + 1)
-/* SSE4.2 or ABM support required */
-#define CpuSSE4_2_Or_ABM (CpuSSE4_1_Or_5 + 1)
 /* 64bit support available, used by -march= in assembler.  */
-#define CpuLM		(CpuSSE4_2_Or_ABM + 1)
+#define CpuLM		(CpuSSE5 + 1)
 /* 64bit support required  */
 #define Cpu64		(CpuLM + 1)
 /* Not supported in the 64bit mode  */
@@ -136,8 +132,6 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpusse5:1;
-      unsigned int cpusse4_1_or_5:1;
-      unsigned int cpusse4_2_or_abm:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
--- binutils/opcodes/i386-opc.tbl.arch	2008-01-03 10:57:31.000000000 -0800
+++ binutils/opcodes/i386-opc.tbl	2008-01-03 14:12:33.000000000 -0800
@@ -1373,11 +1373,11 @@ pmovzxwq, 2, 0x660f3834, None, 3, CpuSSE
 pmovzxdq, 2, 0x660f3835, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pmuldq, 2, 0x660f3828, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 pmulld, 2, 0x660f3840, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-ptest, 2, 0x660f3817, None, 3, CpuSSE4_1_Or_5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-roundpd, 3, 0x660f3a09, None, 3, CpuSSE4_1_Or_5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-roundps, 3, 0x660f3a08, None, 3, CpuSSE4_1_Or_5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-roundsd, 3, 0x660f3a0b, None, 3, CpuSSE4_1_Or_5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-roundss, 3, 0x660f3a0a, None, 3, CpuSSE4_1_Or_5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+ptest, 2, 0x660f3817, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+roundpd, 3, 0x660f3a09, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+roundps, 3, 0x660f3a08, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+roundsd, 3, 0x660f3a0b, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+roundss, 3, 0x660f3a0a, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 
 // SSE4.2 instructions.
 
@@ -1459,7 +1459,7 @@ insertq, 2, 0xf20f79, None, 2, CpuSSE4a,
 insertq, 4, 0xf20f78, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM }
 
 // ABM instructions
-popcnt, 2, 0xf30fb8, None, 2, CpuSSE4_2_Or_ABM, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+popcnt, 2, 0xf30fb8, None, 2, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 lzcnt, 2, 0xf30fbd, None, 2, CpuABM, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 
 // SSE5 instructions
@@ -1722,21 +1722,21 @@ cvtph2ps, 2, 0x0f7a30, None, 3, CpuSSE5,
 cvtps2ph, 2, 0x0f7a31, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,          { RegXMM,          RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex }
 
 // VIA PadLock extensions.
-xstore-rng, 0, 0xfa7, 0xc0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcrypt-ecb, 0, 0xf30fa7, 0xc8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcrypt-cbc, 0, 0xf30fa7, 0xd0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcrypt-ctr, 0, 0xf30fa7, 0xd8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcrypt-cfb, 0, 0xf30fa7, 0xe0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcrypt-ofb, 0, 0xf30fa7, 0xe8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-montmul, 0, 0xf30fa6, 0xc0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xsha1, 0, 0xf30fa6, 0xc8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xsha256, 0, 0xf30fa6, 0xd0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xstore-rng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcrypt-ecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcrypt-cbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcrypt-ctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcrypt-cfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcrypt-ofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+montmul, 0, 0xf30fa6, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xsha1, 0, 0xf30fa6, 0xc8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xsha256, 0, 0xf30fa6, 0xd0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
 // Aliases without hyphens.
-xstorerng, 0, 0xfa7, 0xc0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcryptecb, 0, 0xf30fa7, 0xc8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcryptcbc, 0, 0xf30fa7, 0xd0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcryptctr, 0, 0xf30fa7, 0xd8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcryptcfb, 0, 0xf30fa7, 0xe0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
-xcryptofb, 0, 0xf30fa7, 0xe8, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xstorerng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcryptecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcryptcbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcryptctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcryptcfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xcryptofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
 // Alias for xstore-rng.
-xstore, 0, 0xfa7, 0xc0, 2, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }
+xstore, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 }



More information about the Binutils mailing list